Block Marking and Updating Coding in Test Data Compression for SoC. - Lei Zhang 008; Huaguo Liang; Wenfa Zhan; Cuiyun Jiang (ATS, 2007)

A Routing Algorithm for Random Error Tolerance in Network-on-Chip. - Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (HCI (4), 2007)

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. - Lei Zhang 008; Yinhe Han 001; Qiang Xu 001; Xiaowei Li 001 (DATE, 2008)

A teleoperation system for mobile robot with whole viewpoints virtual scene for situation awareness. - Lei Zhang 008; Yingzi Li; Peihua Zhang; Na Yang; Zheng Li 006; Xueshan Gao (ROBIO, 2008)

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. - Song Jin; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001; Guihai Yan (Asian Test Symposium, 2009)

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (PRDC, 2009)

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. - Lei Zhang 008; Yinhe Han 001; Qiang Xu 001; Xiaowei Li 001; Huawei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. - Lei Zhang 008; Yue Yu; Jianbo Dong; Yinhe Han 001; Shangping Ren; Xiaowei Li 001 (DATE, 2010)

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2010)

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (J. Syst. Archit., 2010)

A Novel x -ploiting Strategy for Improving Performance of Test Data Compression. - Maoxiang Yi; Huaguo Liang; Lei Zhang 008; Wenfa Zhan (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

A resilient on-chip router design through data path salvaging. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Jun Liu; Xiaowei Li 001 (Asian Test Symposium, 2011)

Wear rate leveling: lifetime enhancement of PRAM with endurance variation. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Ying Wang 001; Xiaowei Li 001 (DAC, 2011)

Flex memory: Exploiting and managing abundant off-chip optical bandwidth. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2011)

A greedy approach to tolerate defect cores for multimedia applications. - Ke Yue; Soumia Ghalim; Zheng Li 006; Frank Lockom; Shangping Ren; Lei Zhang 008; Xiaowei Li 001 (ESTIMedia, 2011)

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC. - Ke Yue; Frank Lockom; Zheng Li 006; Soumia Ghalim; Shangping Ren; Lei Zhang 008; Xiaowei Li 001 (ASP-DAC, 2012)

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. - Jianliang Gao; Jianxin Wang; Yinhe Han 001; Lei Zhang 008; Xiaowei Li 001 (DATE, 2012)

An Elastic Architecture Adaptable to Millions of Application Scenarios. - Yunji Chen; Tianshi Chen 002; Qi Guo 001; Zhiwei Xu 002; Lei Zhang 008 (NPC, 2012)

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router. - Yinhe Han 001; Cheng Liu 008; Hang Lu; Wen-Bo Li; Lei Zhang 008; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications. - Peng Chen 004; Lei Zhang 008; Yinhe Han 001; Yunji Chen (J. Comput. Sci. Technol., 2014)

Reinventing Memory System Design for Many-Accelerator Architecture. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001 (J. Comput. Sci. Technol., 2014)

An Elastic Architecture Adaptable to Various Application Scenarios. - Yue Wu; Yunji Chen; Tianshi Chen 002; Qi Guo 001; Lei Zhang 008 (J. Comput. Sci. Technol., 2014)

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

Neuromorphic accelerators: a comparison between neuroscience and machine-learning approaches. - Zidong Du; Daniel D. Ben-Dayan Rubin; Yunji Chen; Liqiang He; Tianshi Chen 002; Lei Zhang 008; Chengyong Wu; Olivier Temam (MICRO, 2015)

Economizing TSV Resources in 3-D Network-on-Chip Design. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Binzhang Fu; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Data Remapping for Static NUCA in Degradable Chip Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Cambricon-X: An accelerator for sparse neural networks. - Shijin Zhang; Zidong Du; Lei Zhang 008; Huiying Lan; Shaoli Liu; Ling Li 001; Qi Guo 001; Tianshi Chen 002; Yunji Chen (MICRO, 2016)

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Lei Zhang 008; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

The Φ-stack for smart web of things. - Zhiwei Xu 002; Xiaohui Peng 002; Lei Zhang 008; Dong Li 008; Ninghui Sun (SmartIoT@SEC, 2017)

BENCHIP: Benchmarking Intelligence Processors. - Jinhua Tao; Zidong Du; Qi Guo 001; Huiying Lan; Lei Zhang 008; Shengyuan Zhou; Cong Liu; Hai-Feng Liu; Shan Tang; Allen Rush; Willian Chen; Shaoli Liu; et al. (CoRR, 2017)

RL and ANN Based Modular Path Planning Controller for Resource-Constrained Robots in the Indoor Complex Dynamic Environment. - Zakir Ullah; Zhiwei Xu 002; Lei Zhang 008; Libo Zhang 001; Waheed Ullah (IEEE Access, 2018)

BenchIP: Benchmarking Intelligence Processors. - Jinhua Tao; Zidong Du; Qi Guo 001; Huiying Lan; Lei Zhang 008; Shengyuan Zhou; Lingjie Xu; Cong Liu; Hai-Feng Liu; Shan Tang; Allen Rush; Willian Chen; et al. (J. Comput. Sci. Technol., 2018)

A Robust Localization, Slip Estimation, and Compensation System for WMR in the Indoor Environments. - Zakir Ullah; Zhiwei Xu 002; Lei Zhang 008; Libo Zhang 001 (Symmetry, 2018)

TDSNN: From Deep Neural Networks to Deep Spike Neural Networks with Temporal-Coding. - Lei Zhang 008; Shengyuan Zhou; Tian Zhi; Zidong Du; Yunji Chen (AAAI, 2019)

Resilient Neural Network Training for Accelerators with Computing Errors. - Dawen Xu 002; KouZi Xing; Cheng Liu 008; Ying Wang 001; Yulin Dai; Long Cheng 003; Huawei Li 001; Lei Zhang 008 (ASAP, 2019)

OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs. - Cheng Liu 008; Xinyu Chen 001; Bingsheng He; Xiaofei Liao; Ying Wang 001; Lei Zhang 008 (FPT, 2019)

Modeling of Mixing Uniformity for Food With Special Medicinal Purposes Based on Chinese Herbal Medicine. - Ke Han; Lei Zhang 008; Ying Wang 001; Miao Wang; Mian Guo; Huan Li; Yu Zhang 027; Ming Zhao; Qian Zhao; Chunyu Wang; Rui Zhang 040 (IEEE Access, 2019)

Correlation of Gut Microbiome Between ASD Children and Mothers and Potential Biomarkers for Risk Assessment. - Ning Li; Junjie Yang; Jiaming Zhang; Cheng Liang 001; Ying Wang 001; Bin Chen; Changying Zhao; Jingwen Wang; Guangye Zhang; Dongmei Zhao; Yi Liu; Lehai Zhang; et al. (Genom. Proteom. Bioinform., 2019)

Ecosystem of Things: Hardware, Software, and Architecture. - Lu Chao; Xiaohui Peng 002; Zhiwei Xu 002; Lei Zhang 008 (Proc. IEEE, 2019)

Addressing Sparsity in Deep Neural Networks. - Xuda Zhou; Zidong Du; Shijin Zhang; Lei Zhang 008; Huiying Lan; Shaoli Liu; Ling Li 001; Qi Guo 001; Tianshi Chen 002; Yunji Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Lei Zhang 008; Kwang-Ting Cheng (ASAP, 2020)

RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM Accelerator. - Songyun Qu; Bing Li 017; Ying Wang 001; Dawen Xu 002; Xiandong Zhao; Lei Zhang 008 (DAC, 2020)

BitPruner: Network Pruning for Bit-serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (DAC, 2020)

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. - Dawen Xu 002; Kexin Chu; Cheng Liu 008; Ying Wang 001; Lei Zhang 008; Huawei Li 001 (DATE, 2020)

You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design. - Weiwei Chen; Ying Wang 001; Shuang Yang; Chen Liu; Lei Zhang 008 (DATE, 2020)

Towards Best-effort Approximation: Applying NAS to General-purpose Approximate Computing. - Weiwei Chen; Ying Wang 001; Shuang Yang; Chen Liu; Lei Zhang 008 (DATE, 2020)

Multi-task Scheduling for PIM-based Heterogeneous Computing System. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Xianzhong Zhou; Lei Zhang 008; Huaguo Liang; Huawei Li 001 (ACM Great Lakes Symposium on VLSI, 2020)

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators. - Dawen Xu 002; Cheng Chu; Qianlong Wang; Cheng Liu 008; Ying Wang 001; Lei Zhang 008; Huaguo Liang; Kwang-Ting Cheng (ICCD, 2020)

Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware. - Xiandong Zhao; Ying Wang 001; Xuyi Cai; Cheng Liu 008; Lei Zhang 008 (ICLR, 2020)

Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach. - Dawen Xu 002; Cheng Liu 008; Ying Wang 001; Kaijie Tu; Bingsheng He; Lei Zhang 008 (IEEE Trans. Computers, 2020)

VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack. - Hao Lv; Bing Li 017; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ASP-DAC, 2021)

An Intelligent Video Processing Architecture for Edge-cloud Video Streaming. - Chengsi Gao; Ying Wang 001; Weiwei Chen; Lei Zhang 008 (DAC, 2021)

ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator. - Songyun Qu; Bing Li 017; Ying Wang 001; Lei Zhang 008 (DAC, 2021)

Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization. - Mengdi Wang; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (DAC, 2021)

Tenet: A Neural Network Model Extraction Attack in Multi-core Architecture. - Chengsi Gao; Bing Li 017; Ying Wang 001; Weiwei Chen; Lei Zhang 008 (ACM Great Lakes Symposium on VLSI, 2021)

MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design. - Mengdi Wang; Bing Li 017; Ying Wang 001; Cheng Liu 008; Xiaohan Ma; Xiandong Zhao; Lei Zhang 008 (ACM Great Lakes Symposium on VLSI, 2021)

PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices. - Yuquan He; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ICRA, 2021)

NASA: Accelerating Neural Network Design with a NAS Processor. - Xiaohan Ma; Chang Si; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ISCA, 2021)

Optimus: towards optimal layer-fusion on deep learning processors. - Xuyi Cai; Ying Wang 001; Lei Zhang 008 (LCTES, 2021)

CHaNAS: coordinated search for network architecture and scheduling policy. - Weiwei Chen; Ying Wang 001; Gangliang Lin; Chengsi Gao; Cheng Liu 008; Lei Zhang 008 (LCTES, 2021)

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Shuang Zhao; Lei Zhang 008; Huaguo Liang; Huawei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Processing-in-SRAM acceleration for ultra-low power visual 3D perception. - Yuquan He; Songyun Qu; Gangliang Lin; Cheng Liu 008; Lei Zhang 008; Ying Wang 001 (DAC, 2022)

Winograd convolution: a perspective from fault tolerance. - Xinghua Xue; Haitong Huang; Cheng Liu 008; Tao Luo 014; Lei Zhang 008; Ying Wang 001 (DAC, 2022)

DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture. - Xuyi Cai; Ying Wang 001; Xiaohan Ma; Yinhe Han 001; Lei Zhang 008 (MICRO, 2022)

Olympus: Reaching Memory-Optimality on DNN Processors. - Xuyi Cai; Ying Wang 001; Kaijie Tu; Chengsi Gao; Lei Zhang 008 (IEEE Trans. Computers, 2022)

Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning. - Weiwei Chen; Ying Wang 001; Ying Xu; Chengsi Gao; Yinhe Han 001; Lei Zhang 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. - Chengsi Gao; Ying Wang 001; Cheng Liu 008; Mengdi Wang; Weiwei Chen; Yinhe Han 001; Lei Zhang 008 (DATE, 2023)

Efficient Supernet Training Using Path Parallelism. - Ying Xu; Long Cheng 003; Xuyi Cai; Xiaohan Ma; Weiwei Chen; Lei Zhang 008; Ying Wang 001 (HPCA, 2023)

Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. - Xinghua Xue; Cheng Liu 008; Haitong Huang; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

IVP: An Intelligent Video Processing Architecture for Video Streaming. - Chengsi Gao; Ying Wang 001; Yinhe Han 001; Weiwei Chen; Lei Zhang 008 (IEEE Trans. Computers, 2023)

Optimus: An Operator Fusion Framework for Deep Neural Networks. - Xuyi Cai; Ying Wang 001; Lei Zhang 008 (ACM Trans. Embed. Comput. Syst., 2023)

A Framework for Neural Network Architecture and Compile Co-optimization. - Weiwei Chen; Ying Wang 001; Ying Xu; Chengsi Gao; Cheng Liu 008; Lei Zhang 008 (ACM Trans. Embed. Comput. Syst., 2023)

S$^{2}$ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms. - Yuquan He; Long Zhang; Cheng Liu 008; Lei Zhang 008; Ying Wang 001 (IEEE Robotics Autom. Lett., 2023)

Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System. - Hao Lv; Bing Li 017; Lei Zhang 008; Cheng Liu 008; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Network Pruning for Bit-Serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators. - Songyun Qu; Bing Li 017; Shixin Zhao; Lei Zhang 008; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. - Xinghua Xue; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Soft Error Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators. - Songyun Qu; Shixin Zhao; Bing Li 017; Yintao He; Xuyi Cai; Lei Zhang 008; Ying Wang 001 (ASPLOS (2), 2024)

DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. - Mingkai Chen; Tianhua Han; Cheng Liu 008; Shengwen Liang; Kuai Yu; Lei Dai; Ziming Yuan; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

PDG: A Prefetcher for Dynamic Graph Updating. - Xinmiao Zhang 004; Cheng Liu 008; Jiacheng Ni; Yuanqing Cheng; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. - Mingkai Chen; Cheng Liu 008; Shengwen Liang; Lei He 016; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

HisOrder: A Historical Frontier-Aware Graph Reordering for Efficient BFS. - Xinmiao Zhang 004; Xiaorong Qin; Lei Zhang 008; Cheng Liu 008 (FCPC@PPOPP, 2025)

FrontOrder: Frontier-Guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (ICDE, 2025)

Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Hayden Kwok-Hay So; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IPDPS, 2025)

Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation. - Xinmiao Zhang 004; Zheng Feng; Shengwen Liang; Xinyu Chen 001; Lei Zhang 008; Cheng Liu 008 (LCTES, 2025)

Frontier-guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (PPoPP, 2025)

Improving DNN Accuracy on MLC PIM via Non-Ideal PIM Device Fine-Tuning. - Hao Lv; Lei Zhang 008; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

In-Situ NAS: A Plug-and-Search Neural Architecture Search Framework Across Hardware Platforms. - Hao Lv; Lei Zhang 008; Ying Wang 001 (IEEE Trans. Computers, 2025)