Extremely scaled silicon nano-CMOS devices. - Leland Chang; Yang-Kyu Choi; Daewon Ha; Pushkar Ranade; Shiying Xiong; Jeffrey Bokor; Chenming Hu; Tsu-Jae King 001 (Proc. IEEE, 2003)

Ultralow-voltage, minimum-energy CMOS. - Scott Hanson; Bo Zhai; Kerry Bernstein; David T. Blaauw; Andres Bryant; Leland Chang; Koushik K. Das; Wilfried Haensch; Edward J. Nowak; Dennis Sylvester (IBM J. Res. Dev., 2006)

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. - Leland Chang; Robert K. Montoye; Yutaka Nakamura; Kevin Batson; Richard J. Eickemeyer; Robert H. Dennard; Wilfried Haensch; Damir Jamsek (IEEE J. Solid State Circuits, 2008)

Low power circuit design based on heterojunction tunneling transistors (HETTs). - Daeyeon Kim; Yoonmyung Lee; Jin Cai; Isaac Lauer; Leland Chang; Steven J. Koester; Dennis Sylvester; David T. Blaauw (ISLPED, 2009)

A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS. - Masood Qazi; Kevin Stawiasz; Leland Chang; Anantha P. Chandrakasan (ISSCC, 2010)

Practical Strategies for Power-Efficient Computing Technologies. - Leland Chang; David J. Frank; Robert K. Montoye; Steven J. Koester; Brian L. Ji; Paul W. Coteus; Robert H. Dennard; Wilfried Haensch (Proc. IEEE, 2010)

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. - Jae-sun Seo; Bernard Brezzo; Yong Liu 023; Benjamin D. Parker; Steven K. Esser; Robert K. Montoye; Bipin Rajendran; José A. Tierno; Leland Chang; Dharmendra S. Modha; Daniel J. Friedman (CICC, 2011)

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. - Gary S. Ditlow; Robert K. Montoye; Salvatore N. Storino; Sherman M. Dance; Sebastian Ehrenreich; Bruce M. Fleischer; Thomas W. Fox; Kyle M. Holmes; Junichi Mihara; Yutaka Nakamura; Shohji Onishi; Robert Shearer; et al. (ISSCC, 2011)

Future system and memory architectures: Transformations by technology and applications. - Nicky Lu; Leland Chang; Daisaburo Takashima (ISSCC, 2011)

Guest editors' introduction: Nanoscale Memories Pose Unique Challenges. - Chris H. Kim; Leland Chang (IEEE Des. Test Comput., 2011)

A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS. - Masood Qazi; Kevin Stawiasz; Leland Chang; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2011)

Near-threshold operation for power-efficient computing?: it depends... - Leland Chang; Wilfried Haensch (DAC, 2012)

Session 13 overview: High-performance embedded SRAM: Memory subcommittee. - Leland Chang; Michael Clinton (ISSCC, 2012)

F2: VLSI power-management techniques: Principles and applications. - Leland Chang; Shannon Morton; Ken Chang; Jin-Man Han; Piero Malcovati; Vladimir Stojanovic (ISSCC, 2013)

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. - Yong Liu 023; Ping-Hsuan Hsieh; Seongwon Kim; Jae-sun Seo; Robert K. Montoye; Leland Chang; José A. Tierno; Daniel J. Friedman (ISSCC, 2013)

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs). - Yoonmyung Lee; Daeyeon Kim; Jin Cai; Isaac Lauer; Leland Chang; Steven J. Koester; David T. Blaauw; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2013)

ES2: Data centers to support tomorrow's cloud. - Leland Chang; Ajith Amerasekera; Takashi Hashimoto (ISSCC, 2014)

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. - Timothy C. Fischer; Byeong-Gyu Nam; Leland Chang; Tadahiro Kuroda; Michiel A. P. Pertijs (IEEE J. Solid State Circuits, 2014)

1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing. - Jing Li 073; Robert K. Montoye; Masatoshi Ishii; Leland Chang (IEEE J. Solid State Circuits, 2014)

F2: Memory trends: From big data to wearable devices. - Jonathan Chang; Leland Chang; Antoine Dupret; Chulwoo Kim; Fatih Hamzaoglu; Takefumi Yoshikawa (ISSCC, 2015)

Session 17 overview: Embedded memory and DRAM I/O: Memory subcommittee. - Leland Chang; Takefumi Yoshikawa (ISSCC, 2015)

A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple. - Suyoung Bang; Jae-sun Seo; Inhee Lee 001; Seokhyeon Jeong; Nathaniel Ross Pinckney; David T. Blaauw; Dennis Sylvester; Leland Chang (VLSIC, 2015)

Synthesis design strategies for energy-efficient microprocessors. - Ching Zhou; Yu-Shiang Lin; Pong-Fei Lu; Bruce M. Fleischer; David J. Frank; Leland Chang (ICCD, 2016)

A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering. - Suyoung Bang; Jae-sun Seo; Leland Chang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2016)

POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators. - Swagath Venkataramani; Jungwook Choi; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan; Leland Chang (PACT, 2017)

Cognitive Data-Centric Systems. - Leland Chang (ACM Great Lakes Symposium on VLSI, 2017)

Session 12 overview: SRAM. - Fatih Hamzaoglu; Chun Shiah; Leland Chang (ISSCC, 2017)

Session 11 overview: Nonvolatile memory solutions. - Takashi Kono; Ki-Tae Park; Leland Chang (ISSCC, 2017)

Session 23 overview: DRAM, MRAM & DRAM interfaces. - Takefumi Yoshikawa; Seung-Jun Bae; Leland Chang (ISSCC, 2017)

Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors. - Shubham Jain; Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Pierce Chuang; Leland Chang (DAC, 2018)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

Taming the beast: Programming Peta-FLOP class Deep Learning Systems. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Kailash Gopalakrishnan; Leland Chang (ISLPED, 2018)

Session 12 overview: DRAM: Memory subcommittee. - Seung-Jun Bae; Wolfgang Spirkl; Leland Chang (ISSCC, 2018)

Session 11 overview: SRAM: Memory subcommittee. - Jonathan Chang; Chun Shiah; Leland Chang (ISSCC, 2018)

Session 20 overview: Flash-memory solutions: Memory subcommittee. - Ki-Tae Park; Yan Li; Leland Chang (ISSCC, 2018)

Session 30 overview: Emerging memories: Memory and technology directions subcommittees. - Shinichiro Shiratake; Edoardo Charbon; Leland Chang; Makoto Nagata (ISSCC, 2018)

Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees. - Naveen Verma; Fatih Hamzaoglu; Makoto Nagata; Leland Chang (ISSCC, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks. - Shubham Jain; Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Kailash Gopalakrishnan; Leland Chang (DAC, 2019)

Memory and Interconnect Optimizations for Peta-Scale Deep Learning Systems. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Philip Heidelberger; Leland Chang; Kailash Gopalakrishnan (HiPC, 2019)

Performance-driven Programming of Multi-TFLOP Deep Learning Accelerators. - Swagath Venkataramani; Jungwook Choi; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan; Leland Chang (IISWC, 2019)

DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator. - Swagath Venkataramani; Jungwook Choi; Vijayalakshmi Srinivasan; Wei Wang 333; Jintao Zhang; Marcel Schaal; Mauricio J. Serrano; Kazuaki Ishizaki; Hiroshi Inoue; Eri Ogawa; Moriyoshi Ohara; Leland Chang; et al. (IEEE Micro, 2019)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

Deep Compression of Pre-trained Transformer Models. - Naigang Wang; Chi-Chun (Charlie) Liu; Swagath Venkataramani; Sanchari Sen; Chia-Yu Chen; Kaoutar El Maghraoui; Vijayalakshmi Srinivasan; Leland Chang (NeurIPS, 2022)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. - Ankur Agrawal; Monodeep Kar; Kyu-Hyoun Kim; Sergey V. Rylov; Jinwook Jung; Seiji Munetoh; Kohji Hosokawa; Xin Zhang 025; Bahman Hekmatshoartabari; Fabio Carta; Martin Cochet; Robert Casatuta; et al. (VLSI Technology and Circuits, 2023)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)