Global Interconnect Analysis and Optimization for Nanometer Scale VLSI. - Lele Jiang; Junfa Mao (APCCAS, 2006)

Characterization and analysis of pattern dependent variation-aware interconnects for a 65nm technology. - Lele Jiang; Xiaojing Qin; Lifu Chang; Yuhua Cheng (ASICON, 2011)

Device parameter variations of n-MOSFETS with dog-bone layouts in 65nm and 40nm technologies. - Lele Jiang; Song Wen 002; Wei Tai; Wang Lei; Lifu Chang; Yuhua Cheng (ASICON, 2013)

Characteristics of n-MOSFETs with stress effects from neighborhood devices. - Wei Tai; Lele Jiang; Wang Lei; Song Wen 002; Lifu Chang; Yuhua Cheng (ASICON, 2013)