Reduction of Current Mismatch in PLL Charge Pump. - H. Md. Shuaeb Fazeel; Leneesh Raghavan; Chandrasekaran Srinivasaraman; Manish Jain (ISVLSI, 2009)

A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. - Vijay Khawshe; Kapil Vyas; Renu Rangnekar; Prateek Goyal; Vijay Krishna; Kashinath Prabhu; Pravin Kumar Venkatesan; Leneesh Raghavan; Rajkumar Palwai; M. Thrivikraman; Kunal Desai; Abhijit Abhyankar (VLSI Design, 2009)

Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link. - Leneesh Raghavan; Ting Wu 003 (VLSI Design, 2010)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)

A Signal and Offset T&H Frontend for Spinning Hall Sensors with Ping-Pong and Chopping Techniques. - Yongjia Li; Mario Motz; Leneesh Raghavan (ESSCIRC, 2018)

A Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong and Chopping Techniques. - Yongjia Li; Mario Motz; Leneesh Raghavan (IEEE J. Solid State Circuits, 2019)