Energy modeling of coupled interconnects including intrinsic misalignment effects. - Amir Najafi 001; Lennart Bamberg; Ardalan Najafi; Alberto García Ortiz (PATMOS, 2016)

Edge effect aware crosstalk avoidance technique for 3D integration. - Lennart Bamberg; Amir Najafi 001; Alberto García Ortiz (PATMOS, 2017)

Design method for asymmetric 3D interconnect architectures with high level models. - Jan Moritz Joseph; Lennart Bamberg; Sven Wrieden; Dominik Ermel; Alberto García Ortiz; Thilo Pionteck (ReCoSoC, 2017)

Low-Power Coding: Trends and New Challenges. - Alberto García Ortiz; Lennart Bamberg; Amir Najafi 001 (J. Low Power Electron., 2017)

High-Level Energy Estimation for Submicrometric TSV Arrays. - Lennart Bamberg; Alberto García Ortiz (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Coding approach for low-power 3D interconnects. - Lennart Bamberg; Robert Schmidt 003; Alberto García Ortiz (DAC, 2018)

Misalignment-aware delay modeling of narrow on-chip interconnects considering variability. - Amir Najafi 001; Lennart Bamberg; Ardalan Najafi; Alberto García Ortiz (MOCAST, 2018)

Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. - Lennart Bamberg; Jan Moritz Joseph; Robert Schmidt 003; Thilo Pionteck; Alberto García Ortiz (PATMOS, 2018)

Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration. - Lennart Bamberg; Alberto García Ortiz (PATMOS, 2018)

Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. - Jan Moritz Joseph; Lennart Bamberg; Gerald Krell; Imad Hajjar; Alberto García Ortiz; Thilo Pionteck (ReCoSoC, 2018)

Edge effects on the TSV array capacitances and their performance influence. - Lennart Bamberg; Amir Najafi 001; Alberto García Ortiz (Integr., 2018)

System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips. - Jan Moritz Joseph; Dominik Ermel; Lennart Bamberg; Alberto García Ortiz; Thilo Pionteck (ICCD, 2019)

Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips. - Jan Moritz Joseph; Dominik Ermel; Tobias Drewes; Lennart Bamberg; Alberto García-Ortiz; Thilo Pionteck (MOCAST, 2019)

A Coding Approach to Improve the Energy Efficiency of Approximate NoCs. - Amir Najafi 001; Lennart Bamberg; Guillermo Payá Vayá; Alberto García Ortiz (ReCoSoC, 2019)

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. - Jan Moritz Joseph; Lennart Bamberg; Dominik Ermel; Behnam Razi Perjikolaei; Anna Drewes; Alberto García Ortiz; Thilo Pionteck (IEEE Access, 2019)

Integer-Value Encoding for Approximate On-Chip Communication. - Amir Najafi 001; Lennart Bamberg; Ardalan Najafi; Alberto García Ortiz (IEEE Access, 2019)

Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs. - Jan Moritz Joseph; Lennart Bamberg; Imad Hajjar; Behnam Razi Perjikolaei; Alberto García Ortiz; Thilo Pionteck (CoRR, 2019)

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. - Lennart Bamberg; Jan Moritz Joseph; Thilo Pionteck; Alberto García Ortiz (Integr., 2019)

Edge effect aware low-power crosstalk avoidance technique for 3D integration. - Lennart Bamberg; Amir Najafi 001; Alberto García Ortiz (Integr., 2019)

Simulation environment for link energy estimation in networks-on-chip with virtual channels. - Jan Moritz Joseph; Lennart Bamberg; Imad Hajjar; Robert Schmidt 003; Thilo Pionteck; Alberto García Ortiz (Integr., 2019)

A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology. - Sai Pentapati; Lingjun Zhu; Lennart Bamberg; Da Eun Shim; Alberto García Ortiz; Sung Kyu Lim (IEEE Micro, 2019)

Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs. - Lennart Bamberg; Alberto García Ortiz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. - Lennart Bamberg; Alberto García Ortiz; Lingjun Zhu; Sai Pentapati; Da Eun Shim; Sung Kyu Lim (DATE, 2020)

Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. - Lingjun Zhu; Lennart Bamberg; Anthony Agnesina; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Julien Ryckaert; Alberto García-Ortiz; Sung Kyu Lim (IEEE Comput. Archit. Lett., 2020)

Misalignment-aware energy modeling of narrow buses for data encoding schemes. - Amir Najafi 001; Lennart Bamberg; Alberto García Ortiz (Integr., 2020)

Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. - Jan Moritz Joseph; Lennart Bamberg; Geonhwa Jeong; Ruei-Ting Chien; Rainer Leupers; Alberto García-Ortiz; Tushar Krishna; Thilo Pionteck (ASP-DAC, 2021)

Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies. - Lennart Bamberg; Tushar Krishna; Jan Moritz Joseph (NANOCOM, 2021)

NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI. - Jan Moritz Joseph; Murat Sezgin Baloglu; Yue Pan; Rainer Leupers; Lennart Bamberg (NOCS, 2021)

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. - Lingjun Zhu; Lennart Bamberg; Sai Surya Kiran Pentapati; Kyungwook Chang; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Brian Cline; Saurabh Sinha; Xiaoqing Xu; Alberto García-Ortiz; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

ARTS: An adaptive regularization training schedule for activation sparsity exploration. - Zeqi Zhu; Arash Pourtaherian; Luc Waeijen; Lennart Bamberg; Egor Bondarev; Orlando Moreira (DSD, 2022)

Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs. - Jan Moritz Joseph; Lennart Bamberg; Imad Hajjar; Behnam Razi Perjikolaei; Alberto García-Ortiz; Thilo Pionteck (ACM Trans. Model. Comput. Simul., 2022)

Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators. - Lennart Bamberg; Arash Pourtaherian; Luc Waeijen; Anupam Chahar; Orlando Moreira (IEEE Trans. Parallel Distributed Syst., 2023)

Exploiting Neural-Network Statistics for Low-Power DNN Inference. - Lennart Bamberg; Ardalan Najafi; Alberto García Ortiz (IEEE Open J. Circuits Syst., 2024)

VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration. - Shereef Helal; Alberto García Ortiz; Lennart Bamberg (MOCAST, 2025)