Scaling Logic Locking Schemes to Multi-module Hardware Designs. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers; Sascha Kegreiß (ARCS, 2020)

A secure hardware-software solution based on RISC-V, logic locking and microkernel. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers; Massimiliano Giacometti; Sascha Kegreiß (SCOPES, 2020)

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. - Lennart M. Reimann; Luca Hanel; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (ICCD, 2021)

Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. - Dominik Sisejkovic; Lennart M. Reimann; Elmira Moussavi; Farhad Merchant; Rainer Leupers (VLSI-SoC, 2021)

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. - Farhad Merchant; Dominik Sisejkovic; Lennart M. Reimann; Kirthihan Yasotharan; Thomas Grass; Rainer Leupers (VLSID, 2021)

Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Harshit Srivastava; Ahmed Hallawa; Rainer Leupers (ACM J. Emerg. Technol. Comput. Syst., 2021)

Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. - Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá; Christoph Riggers; Oliver Renke; Till Fiedler; Jakob Marten; Tobias Stuckenberg; Holger Blume; Christian Weis; Lukas Steiner; Chirag Sudarshan; et al. (DATE, 2023)

Quantitative Information Flow for Hardware: Advancing the Attack Landscape. - Lennart M. Reimann; Sarp Erdönmez; Dominik Sisejkovic; Rainer Leupers (LASCAS, 2023)

Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. - Lennart M. Reimann; Felix Staudigl; Rainer Leupers (NEWCAS, 2023)

Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow's Advanced Memory Range Feature. - Lennart M. Reimann; Jonathan Wiesner; Karol Jaszczyk; Chiara Ghinami; Dominik Germek; Farhad Merchant; Rainer Leupers (VLSI-SoC (Selected Papers), 2023)

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. - Lennart M. Reimann; Jonathan Wiesner; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (VLSI-SoC, 2023)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. - Lennart M. Reimann; Anschul Prashar; Chiara Ghinami; Rebecca Pelke; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (CoRR, 2024)

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction. - Lennart M. Reimann; Yadu Madhukumar Variyar; Lennet Huelser; Chiara Ghinami; Dominik Germek; Rainer Leupers (CoRR, 2024)

Static Global Register Allocation for Dynamic Binary Translators. - Niko Zurstraßen; Nils Bosbach; Lennart M. Reimann; Rainer Leupers (DATE, 2025)

The Impact of Logic Locking on Confidentiality: An Automated Evaluation. - Lennart M. Reimann; Evgenii Rezunov; Dominik Germek; Luca Collini; Christian Pilato; Ramesh Karri; Rainer Leupers (ISQED, 2025)

Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads. - Rebecca Pelke; Nils Bosbach; Lennart M. Reimann; Rainer Leupers (CoRR, 2025)

Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer. - Rebecca Pelke; José Cubero-Cascante; Nils Bosbach; Niklas Degener; Florian Idrizi; Lennart M. Reimann; Jan Moritz Joseph; Rainer Leupers (CoRR, 2025)