Pipelined SHA-3 Implementations on FPGA: Architecture and Performance Analysis. - Harris E. Michail; Lenos Ioannou; Artemios G. Voyiatzis (CS2@HiPEAC, 2015)

High performance pipelined FPGA implementation of the SHA-3 hash algorithm. - Lenos Ioannou; Harris E. Michail; Artemios G. Voyiatzis (MECO, 2015)

Network Intrusion Detection Using Neural Networks on FPGA SoCs. - Lenos Ioannou; Suhaib A. Fahmy (FPL, 2019)

Neural Network Overlay Using FPGA DSP Blocks. - Lenos Ioannou; Suhaib A. Fahmy (FPL, 2019)

Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration. - Lenos Ioannou; Suhaib A. Fahmy (FPT, 2019)

High Throughput Spatial Convolution Filters on FPGAs. - Lenos Ioannou; Abdullah Al-Dujaili; Suhaib A. Fahmy (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Exploring the capabilities of FPGA DSP blocks in neural network accelerators. - Lenos Ioannou (2021)

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs. - Lenos Ioannou; Suhaib A. Fahmy (ACM Trans. Reconfigurable Technol. Syst., 2023)