Scheduling Policy Costs on a JAVA Microcontroller. - Leomar S. da Rosa Jr.; Flávio Rech Wagner; Luigi Carro; Alexandre Carissimi; André Inácio Reis (OTM Workshops, 2003)

Fast disjoint transistor networks from BDDs. - Leomar S. da Rosa Jr.; Felipe S. Marques 001; Tiago Muller Gil Cardoso; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (SBCCI, 2006)

DAG based library-free technology mapping. - Felipe S. Marques 001; Leomar S. da Rosa Jr.; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2007)

A comparative study of CMOS gates with minimum transistor stacks. - Leomar S. da Rosa Jr.; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Felipe Ribeiro Schneider (SBCCI, 2007)

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. - Paulo F. Butzen; Leomar S. da Rosa Jr.; Erasmo J. D. Chiappetta Filho; Dionatan S. Moura; André Inácio Reis; Renato P. Ribas (ACM Great Lakes Symposium on VLSI, 2008)

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. - Tiago Muller Gil Cardoso; Leomar S. da Rosa Jr.; Felipe de Souza Marques; Renato P. Ribas; André Inácio Reis (ISQED, 2008)

Switch level optimization of digital CMOS gate networks. - Leomar S. da Rosa Jr.; Felipe Ribeiro Schneider; Renato P. Ribas; André Inácio Reis (ISQED, 2009)

Boolean factoring with multi-objective goals. - Mayler G. A. Martins; Leomar S. da Rosa Jr.; Anders B. Rasmussen; Renato P. Ribas; André Inácio Reis (ICCD, 2010)

SwitchCraft: a framework for transistor network design. - Vinicius Callegaro; Felipe de Souza Marques; Carlos Eduardo Klock; Leomar Soares da Rosa Jr.; Renato P. Ribas; André Inácio Reis (SBCCI, 2010)

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. - Paulo F. Butzen; Leomar S. da Rosa Jr.; Erasmo J. D. Chiappetta Filho; André Inácio Reis; Renato P. Ribas (Microelectron. J., 2010)

Tests and Performance Analysis of Media Processing Implementations for the Middleware of Brazilian Digital TV System Using Different Scenarios. - Tiago Henrique Trojahn; Juliano Lucas Gonçalves; Júlio C. B. de Mattos; Luciano Volcan Agostini; Leomar Soares da Rosa Jr. (MUE, 2011)

A comparative analysis of media processing component implementations for the Brazilian digital TV middleware. - Tiago Henrique Trojahn; Juliano Lucas Gonçalves; Júlio Carlos Balzano de Mattos; Luciano Volcan Agostini; Leomar Soares da Rosa Jr. (Int. J. Inf. Technol. Commun. Convergence, 2011)

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2012)

Evaluating two implementations of the component responsible for decoding video and audio in the Brazilian digital TV middleware. - Tiago Henrique Trojahn; Juliano Lucas Gonçalves; Júlio Carlos Balzano de Mattos; Luciano Volcan Agostini; Leomar Soares da Rosa Jr. (Multim. Tools Appl., 2012)

Efficient transistor-level design of CMOS gates. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (ACM Great Lakes Symposium on VLSI, 2013)

Transistor-level optimization of CMOS complex gates. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (LASCAS, 2013)

Improving the methodology to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (SBCCI, 2013)

A new general purpose line probe routing algorithm. - Stephano Machado Moreira Goncalves; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (ICECS, 2014)

Exploring Independent Gates in FinFET-Based Transistor Network Generation. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar Soares da Rosa Jr. (SBCCI, 2014)

Evaluating Geometric Aspects of Non-Series-Parallel Cells. - Maicon Schneider Cardoso; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (SBCCI, 2015)

Topological characteristics of logic networks generated by a graph-based methodology. - Maicon Schneider Cardoso; Regis Zanandrea; Renato Souza de Souza; Joao Junior da Silva Machado; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (LASCAS, 2016)

Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. - Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Adriel Mota Ziesemer; Felipe S. Marques 001; Leomar S. da Rosa Jr. (LASCAS, 2016)

Physical design of supergate cells aiming geometrical optimizations. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Regis Zanandrea; Renato Souza de Souza; Leomar S. da Rosa; Felipe de Souza Marques (MWSCAS, 2016)

Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. - Gustavo H. Smaniotto; Matheus T. Moreira; Adriel Mota Ziesemer; Felipe S. Marques 001; Leomar S. da Rosa (MWSCAS, 2016)

Graph-Based Transistor Network Generation Method for Supergate Design. - Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A post-processing methodology to improve the automatic design of CMOS gates at layout-level. - Gustavo H. Smaniotto; Regis Zanandrea; Maicon Schneider Cardoso; Renato Souza de Souza; Matheus T. Moreira; Felipe S. Marques 001; Leomar S. da Rosa Jr. (ICECS, 2017)

A survey of path search algorithms for VLSI detailed routing. - Stephano Machado Moreira Goncalves; Leomar S. da Rosa Jr.; Felipe de Souza Marques (ISCAS, 2017)

Post-processing of supergate networks aiming cell layout optimization. - Gustavo H. Smaniotto; Regis Zanandrea; Maicon Schneider Cardoso; Renato Souza de Souza; Matheus T. Moreira; Felipe S. Marques 001; Leomar S. da Rosa Jr. (ISCAS, 2017)

Transistor placement strategies for non-series-parallel cells. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Leomar S. da Rosa; Felipe de Souza Marques (MWSCAS, 2017)

Transistor Count Optimization in IG FinFET Network Design. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. - Matheus F. Pontes; Paulo F. Butzen; Rafael B. Schvittz; Leomar S. da Rosa Jr.; Denis Teixeira Franco (ICECS, 2018)

Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. - Rafael B. Schvittz; Denis Teixeira Franco; Leomar S. da Rosa Jr.; Paulo F. Butzen (ICECS, 2018)

Reliability evaluation of circuits designed in multi- and single-stage versions. - Rafael B. Schvittz; Matheus F. Pontes; Cristina Meinhardt; Denis Teixeira Franco; Lirida A. B. Naviner; Leomar S. da Rosa; Paulo F. Butzen (LASCAS, 2018)

Area-Aware Design of Static CMOS Complex Gates. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Andrei A. O. Bubolz; Leomar S. da Rosa Jr.; Felipe S. Marques 001 (NEWCAS, 2018)

A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing. - Stéphano M. M. Gonçalves; Leomar S. da Rosa; Felipe S. de Marques 001 (NEWCAS, 2018)

Libra: An Automatic Design Methodology for CMOS Complex Gates. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Andrei A. O. Bubolz; Matheus T. Moreira; Leomar S. da Rosa Jr.; Felipe de Souza Marques (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing. - Stéphano M. M. Gonçalves; Leomar S. da Rosa; Felipe S. de Marques 001 (ISCAS, 2019)

Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. - Vitor G. Lima; Guilherme Paim; Leandro M. G. Rocha; Leomar S. da Rosa Jr.; Felipe S. Marques 001; Eduardo A. C. da Costa; Vinícius V. Camargo; Rafael Soares; Sergio Bampi (ISCAS, 2019)

An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. - Rafael B. Schvittz; Denis Teixeira Franco; Leomar S. da Rosa; Paulo F. Butzen (VLSI-SoC (Selected Papers), 2019)

Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies. - Henrique Kessler; Plinio Finkenauer; Thiago H. Both; Leomar Soares da Rosa Jr.; Vinícius V. Camargo (ISCAS, 2020)

Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients. - Rafael B. Schvittz; Paulo F. Butzen; Leomar S. da Rosa (ITC, 2020)

A Straightforward Methodology for QCA Circuits Design. - Julio Saraçol Domingues Júnior; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (SBCCI, 2020)

DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing. - Stéphano M. M. Gonçalves; Leomar S. da Rosa Jr.; Felipe de Souza Marques (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling. - Stephano Machado Moreira Goncalves; Leomar S. da Rosa Jr.; Felipe S. Marques 001 (ACM Trans. Design Autom. Electr. Syst., 2021)

Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions. - Henrique Kessler; Marcelo Schiavon Porto; Leomar Soares da Rosa Jr.; Vinícius V. Camargo (ISCAS, 2022)

Fault Tolerance Evaluation of Different Majority Voter Designs. - Ingrid F. V. Oliveira; Matheus F. Pontes; Rafael B. Schvittz; Leomar S. da Rosa Jr.; Paulo F. Butzen; Rafael Iankowski Soares (ISCAS, 2022)

The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis. - Matheus F. Pontes; Ingrid F. V. Oliveira; Rafael B. Schvittz; Leomar Soares da Rosa Jr.; Paulo F. Butzen (ISCAS, 2022)

Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. - Henrique Kessler; Murilo Bohlke; Leomar S. da Rosa; Marcelo Schiavon Porto; Vinícius V. Camargo (LASCAS, 2022)

A Fast Approximate Function Generation Method to ATMR Architecture. - Guilherme B. Manske; Clayton R. Farias; Paulo F. Butzen; Leomar S. da Rosa (LASCAS, 2022)

Migortho: A Design Automation Flow for QCA Circuits. - Julio Saraçol Domingues Júnior; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (IEEE Des. Test, 2022)

Alfaba: A Tangible Solution to Support Brazilian Dyslexic Students in their Literacy Process. - Laura Quevedo Jurgina; Lui Gill Aquini; Rafael Iankowski Soares; Leomar Soares da Rosa Jr.; Marilton Sanchotene de Aguiar; Tiago Thompsen Primo (EDUCON, 2023)

Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems. - Tiago R. Balen; Carlos J. González; Ingrid F. V. Oliveira; Leomar S. da Rosa Jr.; Rafael Iankowski Soares; Rafael B. Schvittz; Nemitala Added; Eduardo L. A. Macchione; Vitor A. P. Aguiar; Marcilei Aparecida Guazzelli; Nilberto H. Medina; Paulo F. Butzen (J. Electron. Test., 2023)