A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates. - Rafael B. Schvittz; Denis Teixeira Franco; Leomar Soares; Paulo Francisco Butzen (VLSI-SoC, 2019)

Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation. - Rafael B. Schvittz; Leomar Soares; Paulo Francisco Butzen (VLSI-SoC, 2019)