Concurrent Off-Phase Built-in Self-Test of Dormant Logic. - Leon J. Sigal; Charles R. Kime (ITC, 1988)

A Radix-8 CMOS S/390 Multiplier. - Eric M. Schwarz; Robert M. Averill III; Leon J. Sigal (IEEE Symposium on Computer Arithmetic, 1997)

High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. - James D. Warnock; Leon J. Sigal; Brian W. Curran; Yuen H. Chan (ICCD, 1997)

CMOS floating-point unit for the S/390 Parallel Enterprise Server G4. - Eric M. Schwarz; Leon J. Sigal; Thomas J. McPherson (IBM J. Res. Dev., 1997)

Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. - Leon J. Sigal; James D. Warnock; Brian W. Curran; Yuen H. Chan; Peter J. Camporese; Mark D. Mayo; William V. Huott; Daniel R. Knebel; Ching-Te Chuang; James P. Eckhardt; Philip T. Wu (IBM J. Res. Dev., 1997)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor. - Dale E. Hoffman; Robert M. Averill III; Brian W. Curran; Yuen H. Chan; Allan H. Dansky; Robert F. Hatch; Timothy G. McNamara; Thomas J. McPherson; Gregory A. Northrop; Leon J. Sigal; Anthony Pelella; Patrick M. Williams (ICCD, 1998)

Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors. - Robert M. Averill III; Keith G. Barkley; Michael A. Bowen; Peter J. Camporese; Allan H. Dansky; Robert F. Hatch; Dale E. Hoffman; Mark D. Mayo; Scott A. McCabe; Timothy G. McNamara; Thomas J. McPherson; Gregory A. Northrop; et al. (IBM J. Res. Dev., 1999)

A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors. - Pong-Fei Lu; Nianzheng Cao; Leon J. Sigal; Pieter Woltgens; Raphael Robertazzi; David F. Heidel (ISLPED, 2006)

Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. - Brian W. Curran; Eric Fluhr; Jose Paredes; Leon J. Sigal; Joshua Friedrich; Yiu-Hing Chan; Charlie Hwang (IBM J. Res. Dev., 2007)

POWER7TM local clocking and clocked storage elements. - James D. Warnock; Leon J. Sigal; Dieter F. Wendel; K. Paul Muller; Joshua Friedrich; Victor V. Zyuban; Ethan H. Cannon; A. J. KleinOsowski (ISSCC, 2010)

A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit. - Xiao Yan Zhang; Yiu-Hing Chan; Robert K. Montoye; Leon J. Sigal; Eric M. Schwarz; Michael Kelly (J. Signal Process. Syst., 2010)

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. - James D. Warnock; Y. Chan; William V. Huott; Sean M. Carey; Michael F. Fee; Huajun Wen; Mary Jo Saccamango; Frank Malgioglio; Patrick J. Meaney; Donald W. Plass; Yuen H. Chan; Mark D. Mayo; et al. (ISSCC, 2011)

5.5GHz system z microprocessor and multi-chip module. - James D. Warnock; Yuen H. Chan; Hubert Harrer; David L. Rude; Ruchir Puri; Sean M. Carey; Gerard Salem; Guenter Mayer; Yiu-Hing Chan; Mark D. Mayo; Adam Jatkowski; Gerald Strevig; et al. (ISSCC, 2013)

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. - James D. Warnock; Yuen H. Chan; Hubert Harrer; Sean M. Carey; Gerard Salem; Doug Malone; Ruchir Puri; Jeffrey A. Zitz; Adam Jatkowski; Gerald Strevig; Ayan Datta; Anne Gattiker; et al. (IEEE J. Solid State Circuits, 2014)

A case study of electromigration reliability: From design point to system operations. - Baozhen Li; K. Paul Muller; James D. Warnock; Leon J. Sigal; Dinesh Badami (IRPS, 2015)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

IBM z13 circuit design and methodology. - James D. Warnock; Christopher J. Berry; Michael H. Wood; Leon J. Sigal; Yun-Chan Myung; Guenter Mayer; Mark D. Mayo; Y. Chan; Frank Malgioglio; Gerald Strevig; Charudhattan Nagarajan; Sean M. Carey; et al. (IBM J. Res. Dev., 2015)

IBM z14™: 14nm microprocessor for the next-generation mainframe. - Christopher J. Berry; James D. Warnock; John Isakson; John Badar; Brian Bell 001; Frank Malgioglio; Guenter Mayer; Dina Hamid; Jesse Surprise; David Wolpert 001; Ofer Geva; Bill Huott; et al. (ISSCC, 2018)

IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors. - David Wolpert 001; Erwin Behnen; Leon J. Sigal; Yuen H. Chan; Gustavo Enrique Téllez; Douglas Bradley; Richard E. Serton; Rajesh Veerabhadraiah; William Ansley; Andrew Bianchi; Nagu Dhanwada; Sungjae Lee; et al. (IBM J. Res. Dev., 2018)

IBM z15: Physical design improvements to significantly increase content in the same technology. - Christopher J. Berry; David Wolpert 001; Brian Bell 001; Adam Jatkowski; Jesse Surprise; Gerald Strevig; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Giora Biran; Dina Hamid; et al. (IBM J. Res. Dev., 2020)

37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability. - David Wolpert 001; Gerry Strevig; Christopher J. Berry; Leon J. Sigal; Bill Huott; Mark Cichanowski; Matthias Pflanz; Tobias Werner 001; Philipp Salz; Nick Jinq; Michael Romain; Iris Leefken; et al. (ISSCC, 2025)