From Network to Artwork. - Leon Stok; G. P. Koster (DAC, 1989)

Interconnect optimisation during data path allocation. - Leon Stok (EURO-DAC, 1990)

Flexible Block-Multiplier Generation. - H. M. A. M. Arts; Jos T. J. van Eijndhoven; Leon Stok (ICCAD, 1991)

False loops through resource sharing. - Leon Stok (ICCAD, 1992)

Foreground memory management in data path synthesis. - Leon Stok; Jochen A. G. Jess (Int. J. Circuit Theory Appl., 1992)

Is high-level synthesis marketable? (panel). - Leon Stok (HLSS, 1994)

Data path synthesis. - Leon Stok (Integr., 1994)

Improving initialization through reversed retiming. - Leon Stok; Ilan Y. Spillinger; Guy Even (ED&TC, 1995)

Efficient use of large don't cares in high-level and logic synthesis. - Reinaldo A. Bergamaschi; Daniel Brand; Leon Stok; Michel R. C. M. Berkelaar; Shiv Prakash (ICCAD, 1995)

Be careful with don't cares. - Daniel Brand; Reinaldo A. Bergamaschi; Leon Stok (ICCAD, 1995)

High-level synthesis in an industrial environment. - Reinaldo A. Bergamaschi; Richard A. O'Connor; Leon Stok; Michael Z. Moricz; Shiv Prakash; Andreas Kuehlmann; D. Sreenivasa Rao (IBM J. Res. Dev., 1995)

BooleDozer: Logic synthesis for ASICs. - Leon Stok; David S. Kung 001; Daniel Brand; Anthony D. Drumm; Andrew J. Sullivan; Lakshmi N. Reddy; Nathaniel Hieter; David J. Geiger; Han Hsun Chao; Peter J. Osler (IBM J. Res. Dev., 1996)

Retiming revisited and reversed. - Guy Even; Ilan Y. Spillinger; Leon Stok (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Timing analysis and optimization: from devices to systems (tutorial). - Anirudh Devgan; Leon Stok; Sandip Kundu (ICCAD, 1997)

Gate-size selection for standard cell libraries. - Frederik Beeftink; Prabhakar Kudva; David S. Kung 001; Leon Stok (ICCAD, 1998)

Don't cares in synthesis: theoretical pitfalls and practical solutions. - Daniel Brand; Reinaldo A. Bergamaschi; Leon Stok (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Wavefront Technology Mapping. - Leon Stok; Andrew J. Sullivan; Mahesh A. Iyer (DATE, 1999)

Timing closure: the solution and its problems. - Raul Camposano; Olivier Coudert; Patrick Groeneveld; Leon Stok; Ralph H. J. M. Otten (ASP-DAC, 2000)

Transformational Placement and Synthesis. - Wilm E. Donath; Prabhakar Kudva; Leon Stok; Paul Villarrubia; Lakshmi N. Reddy; Andrew Sullivan; Kanad Chakraborty (DATE, 2000)

Regularity Driven Logic Synthesis. - Thomas Kutzschebauch; Leon Stok (ICCAD, 2000)

Combinatorial cell design for CMOS libraries. - Frederik Beeftink; Prabhakar Kudva; David S. Kung 001; Ruchir Puri; Leon Stok (Integr., 2000)

Congestion Aware Layout Driven Logic Synthesis. - Thomas Kutzschebauch; Leon Stok (ICCAD, 2001)

Layout Driven Decomposition with Congestion Consideration. - Thomas Kutzschebauch; Leon Stok (DATE, 2002)

Pushing ASIC performance in a power envelope. - Ruchir Puri; Leon Stok; John M. Cohn; David S. Kung 001; David Z. Pan; Dennis Sylvester; Ashish Srivastava; Sarvesh H. Kulkarni (DAC, 2003)

There is life left in ASICs. - Leon Stok; John M. Cohn (ISPD, 2003)

Guest Editorial. - Soha Hassoun; Steven M. Nowick; Leon Stok (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Keeping hot chips cool. - Ruchir Puri; Leon Stok; Subhrajit Bhattacharya (DAC, 2005)

Minimizing power with flexible voltage islands. - Ruchir Puri; David S. Kung 001; Leon Stok (ISCAS (1), 2005)

DAC Highlights. - Sachin S. Sapatnekar; Leon Stok (IEEE Des. Test Comput., 2007)

Variability and New Design Paradigms. - Leon Stok (IEEE Des. Test Comput., 2008)

From restrictive to prescriptive design. - Leon Stok (ASP-DAC, 2009)

EDA challenges and options: investing for the future. - Ruchir Puri; William H. Joyner; Raj Jammy; Ahmed Jerraya; Jan M. Rabaey; Walden C. Rhines; Leon Stok (DAC, 2010)

Developing Parallel EDA Tools [The Last Byte]. - Leon Stok (IEEE Des. Test, 2013)

The Next 25 Years in EDA: A Cloudy Future? - Leon Stok (IEEE Des. Test, 2014)

EDA3.0: Implications to Logic Synthesis. - Leon Stok (Advanced Logic Synthesis, 2018)

Concurrent High Performance Processor Design: From Logic to PD in Parallel. - Leon Stok (ISPD, 2018)

EDA and Quantum Computing: a symbiotic relationship? - Shesha Raghunathan; Leon Stok (IEEE Des. Test, 2020)

EDA and Quantum Computing: The key role of Quantum Circuits. - Leon Stok (ISPD, 2021)

Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. - Sherief Reda; Leon Stok; Pierre-Emmanuel Gaillardon (IEEE Des. Test, 2021)

Quantum Challenges for EDA. - Leon Stok (ISPD, 2023)

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors. - Nicolas Dupuis; Ravi Nair; Shyam Ramji; Sean McClintock; Nishant Chauhan; Priyanka Nagpal; Bart Blaner; Ken Valk; Leon Stok; Ruchir Puri (CoRR, 2025)