Runtime fault recovery protocol for NoC-based MPSoCs. - Eduardo Wächter; Augusto Erichsen; Leonardo Juracy; Alexandre M. Amory; Fernando Moraes 001 (ISQED, 2014)

A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications. - Eduardo Wächter; Augusto Erichsen; Leonardo Juracy; Alexandre M. Amory; Fernando Gehm Moraes (SBCCI, 2014)

XGT4: An industrial grade, open source tester for multi-gigabit networks. - Leonardo Rezende Juracy; Felipe B. Lazzarotto; Daniel V. Pigatto; Ney Laert Vilar Calazans; Fernando Gehm Moraes (ICECS, 2017)

Optimized Design of an LSSD Scan Cell. - Leonardo Rezende Juracy; Matheus Trevisan Moreira; Felipe Augusto Kuentzer; Alexandre de Morais Amory (IEEE Trans. Very Large Scale Integr. Syst., 2017)

On the reuse of timing resilient architecture for testing path delay faults in critical paths. - Felipe A. Kuentzer; Leonardo Rezende Juracy; Alexandre M. Amory (DATE, 2018)

An LSSD Compliant Scan Cell for Flip-Flops. - Leonardo Rezende Juracy; Matheus T. Moreira; Felipe A. Kuentzer; Fernando Gehm Moraes; Alexandre M. Amory (ISCAS, 2018)

Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template. - Felipe A. Kuentzer; Leonardo Rezende Juracy; Matheus T. Moreira; Alexandre M. Amory (SBCCI, 2018)

A DfT Insertion Methodology to Scannable Q-Flop Elements. - Leonardo Rezende Juracy; Matheus T. Moreira; Felipe A. Kuentzer; Alexandre M. Amory (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template. - Felipe A. Kuentzer; Leonardo Rezende Juracy; Matheus T. Moreira; Alexandre M. Amory (ASYNC, 2020)

A Survey of Aging Monitors and Reconfiguration Techniques. - Leonardo Rezende Juracy; Matheus Trevisan Moreira; Alexandre de Morais Amory; Fernando Gehm Moraes (CoRR, 2020)

A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. - Leonardo Rezende Juracy; Matheus T. Moreira; Alexandre M. Amory; Fernando Gehm Moraes (LASCAS, 2021)

A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators. - Leonardo Rezende Juracy; Matheus Trevisan Moreira; Alexandre de Morais Amory; Alexandre F. Hampel; Fernando Gehm Moraes (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Assessment and Optimization of 1D CNN Model for Human Activity Recognition. - Rafael Schild Reusch; Leonardo Rezende Juracy; Fernando Gehm Moraes (SBESC, 2022)

A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators. - Leonardo Rezende Juracy; Alexandre de Morais Amory; Fernando Gehm Moraes (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A framework for fast architecture exploration of convolutional neural network accelerators - Leonardo Rezende Juracy (2022)

Deploying Machine Learning in Resource-Constrained Devices for Human Activity Recognition. - Rafael Schild Reusch; Leonardo Rezende Juracy; Fernando Gehm Moraes (SBESC, 2023)

From CNN to DNN Hardware Accelerators: A Survey on Design, Exploration, Simulation, and Frameworks. - Leonardo Rezende Juracy; Rafael Garibotti; Fernando Gehm Moraes (Found. Trends Electron. Des. Autom., 2023)

A Comprehensive Evaluation of Convolutional Hardware Accelerators. - Leonardo Rezende Juracy; Alexandre M. Amory; Fernando Moraes 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Deploying human activity recognition in embedded RISC-V processors. - Willian Analdo Nunes; Rafael Schild Reusch; Lucas Luza; Eduardo Bernardon; Angelo Elias Dalzotto; Leonardo Rezende Juracy; Fernando Gehm Moraes (Des. Autom. Embed. Syst., 2024)