Design of synchronous pipeline digital systems operating in double-edge of the clock. - Duarte Lopes de Oliveira; Tiago S. Curtinhas; Lester de Abreu Faria; Leonardo Romano (LASCAS, 2013)

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers. - Tiago S. Curtinhas; Duarte Lopes de Oliveira; Diego Bompean; Lester de Abreu Faria; Leonardo Romano (LASCAS, 2014)

A novel asynchronous interface with pausible clock for partitioned synchronous modules. - Duarte Lopes de Oliveira; Tiago S. Curtinhas; Lester de Abreu Faria; Leonardo Romano (LASCAS, 2015)

A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm. - Tiago S. Curtinhas; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista; Vitor L. V. Torres; Leonardo Romano (LASCAS, 2019)

A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications. - Higor A. Delsoto; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista; Diego A. Silva; Leonardo Romano (LASCAS, 2019)

An Implementation of Extended Burst-Mode Specifications as Quasi Delay Insensitive State Machines. - Duarte Lopes de Oliveira; Orlando Verducci Jr.; Vitor L. V. Torres; Gracieth Cavalcanti Batista; Robson L. Moreno; Leonardo Romano (LASCAS, 2019)

Synthesis of Asynchronous State Machines from Synchronous Specifications. - Duarte Lopes de Oliveira; Gabriel C. Duarte; Gracieth Cavalcanti Batista; Diego A. Silva; Leonardo Romano (LASCAS, 2020)