Fault modeling and testing of through silicon via interconnections. - Vasileios Gerakis; Leonidas Katselas; Alkis A. Hatzopoulos (IOLTS, 2015)

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. - Leonidas Katselas; Hailong Jiao; Angelos Athanasiadis; Christos Papameletis; Alkis A. Hatzopoulos; Erik Jan Marinissen (PATMOS, 2017)

On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. - Leonidas Katselas; Alkis A. Hatzopoulos; Hailong Jiao; Christos Papameletis; Erik Jan Marinissen (ITC, 2018)

Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. - Kazuki Monta; Leonidas Katselas; Ferenc Fodor; Alkis A. Hatzopoulos; Makoto Nagata; Erik Jan Marinissen (ETS, 2021)

Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. - Kazuki Monta; Leonidas Katselas; Ferenc Fodor; Takuji Miki; Alkis A. Hatzopoulos; Makoto Nagata; Erik Jan Marinissen (IEEE Des. Test, 2022)

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. - Pascal Alexander Hager; Bert Moons; Stefan Cosemans; Ioannis A. Papistas; Bram Rooseleer; Jeroen Van Loon; Roel Uytterhoeven; Florian Zaruba; Spyridoula Koumousi; Milos Stanisavljevic; Stefan Mach; Sebastiaan Mutsaards; et al. (ISSCC, 2024)