An Evolutionary Local Search Algorithm for the Satisfiability Problem. - Levent Aksoy; Ece Olcay Günes (TAINN, 2005)

Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2006)

ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICECS, 2006)

Optimization of Area in Digital FIR Filters using Gate-Level Metrics. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2007)

Minimum number of operations under a general number representation for digital filter synthesis. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (ECCTD, 2007)

Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. - Levent Aksoy; Ece Olcay Günes; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (SiPS, 2007)

An approximate algorithm for the multiple constant multiplications problem. - Levent Aksoy; Ece Olcay Günes (SBCCI, 2008)

Area optimization algorithms in high-speed digital FIR filter synthesis. - Levent Aksoy; Ece Olcay Günes (SBCCI, 2008)

Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Design of low complexity digital FIR filters. - Levent Aksoy; Diego Jaccottet; Eduardo Costa 001 (SBCCI, 2009)

Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DSD, 2010)

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. - Sidinei Ghissoni; Eduardo Costa 001; Cristiano Lazzari; José Monteiro 001; Levent Aksoy; Ricardo Reis 001 (ICECS, 2010)

Design of low-complexity and high-speed digital Finite Impulse Response filters. - Diego Jaccottet; Eduardo Costa 001; Levent Aksoy; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2010)

Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability - Nuno P. Lopes; Levent Aksoy; Vasco Manquinho; José Monteiro 001 (CoRR, 2010)

Search algorithms for the multiple constant multiplications problem: Exact and approximate. - Levent Aksoy; Ece Olcay Günes; Paulo F. Flores (Microprocess. Microsystems, 2010)

Optimization of gate-level area in high throughput Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2011)

Design of low-power multiple constant multiplications using low-complexity minimum depth operations. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Efficient shift-adds design of digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ISCAS, 2011)

A hybrid algorithm for the optimization of area and delay in linear DSP transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2011)

Multiplierless Design of Linear DSP Transforms. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (VLSI-SoC (Selected Papers), 2011)

Finding the optimal tradeoff between area and delay in multiple constant multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Microprocess. Microsystems, 2011)

Design of low-complexity digital finite impulse response filters on FPGAs. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DATE, 2012)

Multiple tunable constant multiplications: Algorithms and applications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICCAD, 2012)

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Integr., 2012)

Optimization Algorithms for the Multiplierless Realization of Linear Transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Exploration of tradeoffs in the design of integer cosine transforms for image compression. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2013)

SIREN: a depth-first search algorithm for the filter design optimization problem. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2013)

Towards the least complex time-multiplexed constant multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2013)

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Optimization of design complexity in time-multiplexed constant multiplications. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (DATE, 2014)

Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ICCD, 2014)

ECHO: A novel method for the multiplierless design of constant array vector multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ISCAS, 2014)

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (Circuits Syst. Signal Process., 2014)

Multiplierless Design of Folded DSP Blocks. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Approximation of multiple constant multiplications using minimum look-up tables on FPGA. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ISCAS, 2015)

Exact and Approximate Algorithms for the Filter Design Optimization Problem. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Signal Process., 2015)

A novel method for the approximation of multiplierless constant matrix vector multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (EURASIP J. Embed. Syst., 2016)

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices. - Levent Aksoy; Mustafa Altun (DATE, 2019)

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling. - Serzat Safaltin; Oguz Gencer; Muhammed Ceylan Morgül; Levent Aksoy; Sebahattin Gurmen; Csaba Andras Moritz; Mustafa Altun (DATE, 2019)

CMOS Implementation of Switching Lattices. - Ismail Cevik; Levent Aksoy; Mustafa Altun (DATE, 2020)

A Novel Method for the Realization of Complex Logic Functions using Switching Lattices. - Levent Aksoy; Mustafa Altun (ISCAS, 2020)

Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks. - Levent Aksoy; Sajjad Parvin; Mohammadreza Esmali Nojehdeh; Mustafa Altun (ISCAS, 2020)

Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks. - Mohammadreza Esmali Nojehdeh; Levent Aksoy; Mustafa Altun (ISVLSI, 2020)

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices. - Levent Aksoy; Mustafa Altun (IEEE Trans. Computers, 2020)

Side-Channel Attacks on Triple Modular Redundancy Schemes. - Felipe Almeida; Levent Aksoy; Jaan Raik; Samuel Pagliarini (ATS, 2021)

High-level Intellectual Property Obfuscation via Decoy Constants. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IOLTS, 2021)

Realization of Logic Functions Using Switching Lattices Under a Delay Constraint. - Levent Aksoy; Nihat Akkan; Herman Sedef; Mustafa Altun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Hardware Obfuscation of Digital FIR Filters. - Levent Aksoy; Alexander Hepp; Johanna Baehr 001; Samuel Pagliarini (DDECS, 2022)

Multiplierless Design of Very Large Constant Multiplications in Cryptography. - Levent Aksoy; Debapriya Basu Roy; Malik Imran; Patrick Karl; Samuel Pagliarini (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches. - Nihat Akkan; Serzat Safaltin; Levent Aksoy; Ismail Cevik; Herman Sedef; Csaba Andras Moritz; Mustafa Altun (IEEE Trans. Emerg. Top. Comput., 2022)

Resynthesis-based Attacks Against Logic Locking. - Felipe Almeida; Levent Aksoy; Quang-Linh Nguyen; Sophie Dupuis; Marie-Lise Flottes; Samuel Pagliarini (ISQED, 2023)

Hybrid Protection of Digital FIR Filters. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Multiplierless Design of High-Speed Very Large Constant Multiplications. - Levent Aksoy; Debapriya Basu Roy; Malik Imran; Samuel Pagliarini (ASPDAC, 2024)

KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking. - Levent Aksoy; Muhammad Yasin; Samuel Pagliarini (DATE, 2024)

CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks. - Levent Aksoy; Muhammad Yasin; Samuel Pagliarini (LATS, 2024)

Late Breaking Results: Is Reconfigurable-Based Obfuscation Secure? - Zain Ul Abideen 002; Levent Aksoy; Samuel Pagliarini (DATE, 2025)

RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking. - Felipe Almeida; Levent Aksoy; Samuel Pagliarini (IEEE Trans. Very Large Scale Integr. Syst., 2025)