Logic Partitioning for Minimizing Gate Arrays. - Chet A. Palesko; Lex A. Akers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A limited-interconnect synthetic neural IC. - Lex A. Akers; Mark R. Walker (ICNN, 1988)

Training a Limited-Interconnect, Synthetic Neural IC. - Mark R. Walker; Siamack Haghighi; A. Afghan; Lex A. Akers (NIPS, 1988)

A CMOS neural network for pattern association. - Mark R. Walker; Paul Hasler; Lex A. Akers (IEEE Micro, 1989)

TRELIS: an optimal unsupervised local training rule. - Siamack Haghighi; Lex A. Akers (IJCNN, 1990)

A retinomorphic VLSI smart sensor for invariant geometric object recognition. - Arun Rao; Lex A. Akers (IJCNN, 1990)

VLSI Implementation of Neural Classifiers. - Arun Rao; Mark R. Walker; Lawrence T. Clark; Lex A. Akers; Robert O. Grondin (Neural Comput., 1990)

A neural processing node with on-chip learning. - James Donald; Lex A. Akers (ISCAS, 1993)

An adaptive neural processing node. - James Donald; Lex A. Akers (IEEE Trans. Neural Networks, 1993)

Pattern Recognition and System Control with a Neural Processor. - James Donald; Lex A. Akers (ISCAS, 1994)

A Temporal Neural System. - Jay Heeb; Lex A. Akers (ISCAS, 1994)

Hardware Implementation of Habituation. - Tony Wang; Lex A. Akers (ISCAS, 1995)

VLSI implementation of rehabituation. - Vijay K. Goru; Lex A. Akers (ICNN, 1996)

A programmable Gaussian node. - Ravishankar Kuppuswamy; Luke Theogarajan; Lex A. Akers (ICNN, 1996)

Silicon models of visual cortical processing. - Luke Theogarajan; Lex A. Akers (ICNN, 1996)

An Electronic Habituation Chip. - Tony Wang; Lex A. Akers (J. Circuits Syst. Comput., 1996)