Optimization of threshold logic networks with ODC-based node merging. - Fu-Lian Wong; Li-Cheng Zheng; Yung-Chih Chen (VLSI-DAT, 2018)

Optimization of Threshold Logic Networks with Node Merging and Wire Replacement. - Yung-Chih Chen; Li-Cheng Zheng; Fu-Lian Wong (ACM Trans. Design Autom. Electr. Syst., 2019)

Don't-Care-Based Node Minimization for Threshold Logic Networks. - Yung-Chih Chen; Hao-Ju Chang; Li-Cheng Zheng (DAC, 2020)

1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. - Li-Cheng Zheng; Hao-Ju Chang; Yung-Chih Chen; Jing-Yang Jou (ASP-DAC, 2021)

Don't-Care-Based Logic Optimization for Threshold Logic. - Yung-Chih Chen; Li-Cheng Zheng; Hao-Ju Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)