A Real Time and Low Cost Hardware Architecture for Video Abstraction System. - Li-Chuan Chang; Yen-Sung Chen; Rung-Wen Liou; Chih-Hung Kuo; Chia-Hung Yeh; Bin-Da Liu (ISCAS, 2007)

System level design of a spatio-temporal video resampling architecture. - Chih-Hung Kuo; Li-Chuan Chang; Zheng-Wei Liu; Bin-Da Liu (ISCAS, 2008)

Low complexity MAD prediction algorithms for rate controllable H.264/AVC hardware encoders. - Li-Chuan Chang; Chih-Hung Kuo; Bin-Da Liu (ISCAS, 2010)

Hardware/Software Codesign of a Low-Cost Rate Control Scheme for H.264/AVC. - Chih-Hung Kuo; Li-Chuan Chang; Kuan-Wei Fan; Bin-Da Liu (IEEE Trans. Circuits Syst. Video Technol., 2010)

A Two-Stage Rate Control Mechanism for RDO-Based H.264/AVC Encoders. - Li-Chuan Chang; Chih-Hung Kuo; Bin-Da Liu (IEEE Trans. Circuits Syst. Video Technol., 2011)