On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. - Li-Chung Hsu; Hung-Ming Chen (ISQED, 2006)

On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques. - Chia-Yi Lin; Li-Chung Hsu; Hung-Ming Chen (IEICE Trans. Electron., 2010)

Design and analysis for ThruChip design for manufacturing (DFM). - Li-Chung Hsu; Yasuhiro Take; Atsutake Kosuge; So Hasegawa; Junichiro Kadamoto; Tadahiro Kuroda (ASP-DAC, 2015)

A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. - Li-Chung Hsu; Junichiro Kadomoto; So Hasegawa; Atsutake Kosuge; Yasuhiro Take; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. - Li-Chung Hsu; Masato Motomura; Yasuhiro Take; Tadahiro Kuroda (IEICE Trans. Electron., 2015)

Analytical thruchip inductive coupling channel design optimization. - Li-Chung Hsu; Junichiro Kadomoto; So Hasegawa; Atsutake Kosuge; Yasuhiro Take; Tadahiro Kuroda (ASP-DAC, 2016)