Determination of radix numbers of the Booth algorithm for the optimized programmable FIR architecture. - Li-Hsun Chen; Wei-Lung Liu; Oscal T.-C. Chen (ISCAS, 2000)

A low-complexity and high-speed Booth-algorithm FIR architecture. - Li-Hsun Chen; Oscal T.-C. Chen (ISCAS (4), 2001)

A reconfigurable digital signal processor architecture for high-efficiency MPEG-4 video encoding. - Li-Hsun Chen; Wei-Lung Liu; Oscal T.-C. Chen; Ruey-Liang Ma (ICME (2), 2002)

A high-efficiency reconfigurable digital signal processor for multimedia computing. - Li-Hsun Chen; Oscal T.-C. Chen; Ruey-Ling Ma (ISCAS (2), 2003)

An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder. - Li-Hsun Chen; Oscal T.-C. Chen; Teng-Yi Wang; Chi-Lung Wang (ISCAS (2), 2004)

A hardware-efficient FIR architecture with input-data and tap folding. - Li-Hsun Chen; Oscal T.-C. Chen (ISCAS (1), 2005)

A multiplication-accumulation computation unit with optimized compressors and minimized switching activities. - Li-Hsun Chen; Oscal T.-C. Chen; Teng-Yi Wang; Yung-Cheng Ma (ISCAS (6), 2005)

A Low-Power Folded Programmable FIR Architecture. - Li-Hsun Chen; Oscal T.-C. Chen (SiPS, 2006)

A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding. - Oscal T.-C. Chen; Li-Hsun Chen (EURASIP J. Adv. Signal Process., 2007)

Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs. - Oscal T.-C. Chen; Li-Hsun Chen; Nai-Wei Lin; Chih-Chang Chen (IEEE Trans. Circuits Syst. Video Technol., 2007)