An FPGA Implementation of Array LDPC Decoder. - Jin Sha; Minglun Gao; Zhongjin Zhang; Li Li 003; Zhongfeng Wang 001 (APCCAS, 2006)

On the Implementation of Virtual Array Using Configuration Plane. - Yongsheng Yin; Li Li 003; Minglun Gao; Gaoming Du; Yu-Kun Song (APPT, 2007)

Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System. - Li Li 003; Yong-Sheng Yin; Minglun Gao (APCCAS, 2008)

Low-complexity shift-LDPC decoder for high-speed communication systems. - Chuan Zhang 001; Li Li 003; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2008)

A scalable distributed memory architecture for Network on Chip. - Yuang Zhang; Li Li 003; Shengguang Yang; Lan Dong; Xiaoxiang Lou; Minglun Gao (APCCAS, 2008)

Towards an Optimal Trade-off of Viterbi Decoder Design. - Jinjin He; Zhongfeng Wang 001; Zhiqiang Cui; Li Li 003 (ISCAS, 2009)

LDPC Decoder Design for IEEE 802.15 Standard. - Jin Sha; Jun Lin 001; Li Li 003; Minglun Gao; Zhongfeng Wang 001 (ISCAS, 2009)

Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications. - Bo Yuan 001; Li Li 003; Jin Sha; Zhongfeng Wang 001 (ISCAS, 2009)

High-throughput GCM VLSI Architecture for IEEE 802.1ae Applications. - Chuan Zhang 001; Li Li 003; Jun Xu 013; Zhongfeng Wang 001 (ISCAS, 2009)

An improved min-sum based column-layered decoding algorithm for LDPC codes. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (SiPS, 2009)

High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications. - Bo Yuan 001; Li Li 003; Zhongfeng Wang 001 (SiPS, 2009)

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. - Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Jin Sha; Minglun Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Decoder Design for RS-Based LDPC Codes. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Area-efficient reed-solomon decoder design for optical communications. - Bo Yuan 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao; Jin Sha; Chuan Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

LDPC decoder design for high rate wireless personal area networks. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Consumer Electron., 2009)

An improved scaled DCT architecture. - Zhigang Wu; Jin Sha; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Consumer Electron., 2009)

Multi-Gb/s LDPC Code Design and Implementation. - Jin Sha; Zhongfeng Wang 001; Minglun Gao; Li Li 003 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Low power decoder design for QC-LDPC codes. - Kai He; Jin Sha; Li Li 003; Zhongfeng Wang 001 (ISCAS, 2010)

Application-level pipelining on Hierarchical NoC. - Wei Yi; Hongbing Pan; Peng Pan; Li Li 003; Minglun Gao; Ning Hou; Gaoming Du; Duoli Zhang (ISCAS, 2010)

Layered decoding for non-binary LDPC codes. - Shuai Zhou; Jin Sha; Li Li 003; Zhongfeng Wang 001 (ISCAS, 2010)

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

An Efficient VLSI Architecture for Nonbinary LDPC Decoders. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. - Chuan Zhang 001; Zhongfeng Wang 001; Jin Sha; Li Li 003; Jun Lin 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm. - Jiawen Wang; Li Li 003; Hongbing Pan; Shuzhuan He; Rong Zhang (ASICON, 2011)

A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications. - Yue Xu; Hongbing Pan; Shuzhuan He; Li Li 003 (Sensors, 2012)

Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction. - Li Li 003; Bo Yuan 001; Zhongfeng Wang 001; Jin Sha; Hongbing Pan; Weishan Zheng (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Performance and power consumption analysis of memory efficient 3D network-on-chip architecture. - Xiao Yu; Li Li 003; Yuang Zhang; Hongbing Pan; Shuzhuan He (ICCA, 2013)

Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC. - Xiao Yu; Li Li 003; Yuang Zhang; Hongbing Pan; Shuzhuan He (ICCA, 2013)

Monolithic H-bridge brushless DC vibration motor driver with a highly sensitive hall sensor in 0.18 μm complementary metal-oxide semiconductor technology. - Yue Xu; Hongbing Pan; Shuzhuan He; Li Li 003 (IET Circuits Devices Syst., 2013)

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips. - Yuang Zhang; Li Li 003; Zhonghai Lu; Axel Jantsch; Yuxiang Fu; Minglun Gao (ISCAS, 2014)

A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs. - Fei Lyu 002; Zhenduo Zhu; Zhenfei Lu; Li Li 003; Jin Sha; Hongbing Pan; Yutong Bi (ISIC, 2014)

A survey of memory architecture for 3D chip multi-processors. - Yuang Zhang; Li Li 003; Zhonghai Lu; Axel Jantsch; Minglun Gao; Hongbing Pan; Feng Han 008 (Microprocess. Microsystems, 2014)

A high performance parallel VLSI design of matrix inversion. - Kun Wang 005; Li Li 003; Feng Han 008; Hongbing Pan; Fan Feng; Xiao Yu (ASICON, 2015)

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links. - Yuxiang Fu; Li Li 003; Yuang Zhang; Hongbing Pan; Feng Han 008; Kun Wang 005 (ASICON, 2015)

An improved FFT architecture optimized for reconfigurable application specified processor. - Feng Han 008; Li Li 003; Kun Wang 005; Fan Feng; Hongbing Pan; Dong Yu (ASICON, 2015)

Exploring stacked main memory architecture for 3D GPGPUs. - Yuang Zhang; Li Li 003; Axel Jantsch; Zhonghai Lu; Minglun Gao; Yuxiang Fu; Hongbing Pan (ASICON, 2015)

Performance Comparison of Cross-Like Hall Plates with Different Covering Layers. - Fei Lyu 002; Zhenyan Zhang; Eng-Huat Toh; Xinfu Liu; Yinjie Ding; Yifan Pan; Chengjie Li; Li Li 003; Jin Sha; Hongbing Pan (Sensors, 2015)

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors. - Yuxiang Fu; Li Li 003; Hongbing Pan; Kun Wang 005; Feng Han 008; Jun Lin 001 (ISCAS, 2016)

A high throughput belief propagation decoder architecture for polar codes. - Jun Lin 001; Jin Sha; Li Li 003; Chenrong Xiong; Zhiyuan Yan 001; Zhongfeng Wang 001 (ISCAS, 2016)

Floating-point operation based reconfigurable architecture for radar processing. - Fan Feng; Li Li 003; Kun Wang 005; Feng Han 008; Baoning Zhang; Guoqiang He (IEICE Electron. Express, 2016)

An ultra-long FFT architecture implemented in a reconfigurable application specified processor. - Feng Han 008; Li Li 003; Kun Wang 005; Fan Feng; Hongbing Pan; Baoning Zhang; Guoqiang He; Jun Lin 001 (IEICE Electron. Express, 2016)

Design and implementation of high performance matrix inversion based on reconfigurable processor. - Kun Wang 005; Li Li 003; Feng Han 008; Fan Feng; Jun Lin 001 (IEICE Electron. Express, 2016)

Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices. - Fei Lyu 002; Xinfu Liu; Yinjie Ding; Eng-Huat Toh; Zhenyan Zhang; Yifan Pan; Zhen Wang; Chengjie Li; Li Li 003; Jin Sha; Hongbing Pan (Sensors, 2016)

Application space exploration of a multi-fabric reconfigurable system. - Fan Feng; Li Li 003; Kun Wang 005; Feng Han 008; Hongbing Pan; Wei Li (ASICON, 2017)

An access pattern based adaptive mapping function for GPGPU scratchpad memory. - Feng Han 008; Li Li 003; Kun Wang 005; Fan Feng; Hongbing Pan; Jin Sha; Jun Lin 001 (IEICE Electron. Express, 2017)

Optimized sorting network for successive cancellation list decoding of polar codes. - Kun Wang 005; Li Li 003; Feng Han 008; Fan Feng; Jun Lin 001; Yuxiang Fu; Jin Sha (IEICE Electron. Express, 2017)

Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors. - Yuxiang Fu; Li Li 003; Kun Wang 005; Chuan Zhang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes. - Wenqing Song; Yuxiang Fu; Qinyu Chen; Li Li 003; Chuan Zhang 001 (ASICON, 2019)

Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning. - Qinyu Chen; Yuxiang Fu; Kaifeng Cheng; Wenqing Song; Zhonghai Lu; Li Li 003; Chuan Zhang 001 (ISCAS, 2019)

Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs. - Yuxiang Fu; Qinyu Chen; Guoqiang He; Kai Chen; Zhonghai Lu; Chuan Zhang 001; Li Li 003 (ISCAS, 2019)

Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC. - Yuxiang Fu; Li Li 003; Hongbing Pan; Kun Wang 005; Fan Feng; Qinyu Chen; Chuan Zhang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Efficient Successive Cancellation Stack Decoder for Polar Codes. - Wenqing Song; Huayi Zhou 002; Kai Niu 001; Zaichen Zhang; Li Li 003; Xiaohu You 001; Chuan Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. - Congyi Zhu; Renrong Liang; Jun Lin 001; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions. - Hui Chen 015; Lin Jiang; Yuanyong Luo; Zhonghai Lu; Yuxiang Fu; Li Li 003; Zongguang Yu (ISCAS, 2020)

Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation. - Hui Chen 015; Kaifeng Cheng; Zhonghai Lu; Yuxiang Fu; Li Li 003 (IEEE Trans. Circuits Syst., 2020)

An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective. - Qinyu Chen; Yan Huang; Rui Sun; Wenqing Song; Zhonghai Lu; Yuxiang Fu; Li Li 003 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation. - Hui Chen 015; Ruiqi Wu; Zhonghai Lu; Yuxiang Fu; Li Li 003; Zongguang Yu (ISCAS, 2021)

Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures. - Qian Gao; Wenqing Song; Zhonghai Lu; Li Li 003; Yuxiang Fu (ISCAS, 2021)

Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes. - Wenqing Song; Yifei Shen; Yuxiang Fu; Chuan Zhang 001; Li Li 003 (ISCAS, 2021)

LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System. - Tong Cheng; Haoyu Du; Li Li 003; Yuxiang Fu (ISOCC, 2021)

Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN. - Menghao Guo; Tong Cheng; Li Li 003; Yuxiang Fu (ISOCC, 2021)

A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers. - Jin Xu; Lin Jiang; Hui Chen 015; Yuxiang Fu; Li Li 003 (ISOCC, 2021)

Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT. - Heping Yang; Hui Chen 015; Yuxiang Fu; Li Li 003 (ISOCC, 2021)

2β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance. - Yonggang Zhang 005; Hui Chen 015; Yuxiang Fu; Li Li 003 (ISOCC, 2021)

IPD capacitor with pseudo-symmetry for isolated differential signal transfer applications. - Minghao Zhou; Li Li 003; Xiangming Fang; Rongxiang Wu (Microelectron. J., 2021)

Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs. - Yuxiang Fu; Chuan Zhang 001; Wenqing Song; Qinyu Chen; Hui Chen 015; Minghao Zhou; Li Li 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions. - Hui Chen 015; Heping Yang; Wenqing Song; Zhonghai Lu; Yuxiang Fu; Li Li 003; Zongguang Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers. - Hui Chen 015; Zongguang Yu; Yonggang Zhang 005; Zhonghai Lu; Yuxiang Fu; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Deep Spiking Neural Network with Ternary Spikes. - Congyi Sun; Qinyu Chen; Yuxiang Fu; Li Li 003 (BioCAS, 2022)

Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems. - Shize Zhou; Yongqi Xue; Siyue Li; Jinlun Ji; Tong Cheng; Li Li 003; Yuxiang Fu (CASES, 2022)

AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks. - Yongqi Xue; Jinlun Ji; Xinyi Li; Siyue Li; Shize Zhou; Tong Cheng; Li Li 003; Yuxiang Fu (ICCD, 2022)

A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography. - Sirui Shen; Wenqing Song; Xinyu Wang; Xinyu Shao; Yuxiang Fu; Zhonghai Lu; Li Li 003 (ISCAS, 2022)

Unsupervised Learning Based on Temporal Coding Using STDP in Spiking Neural Networks. - Congyi Sun; Qinyu Chen; Kai Chen; Guoqiang He; Yuxiang Fu; Li Li 003 (ISCAS, 2022)

Background Noise Adaptive Energy-Efficient Keywords Recognition Processor With Reusable DNN and Reconfigurable Architecture. - Guoqiang He; Xiaoling Ding; Minghao Zhou; Bo Liu 019; Li Li 003 (IEEE Access, 2022)

Huicore: A Generalized Hardware Accelerator for Complicated Functions. - Hui Chen 015; Zongguang Yu; Jin Xu; Lin Jiang; Zhonghai Lu; Yuxiang Fu; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning. - Congyi Sun; Haohan Sun; Jin Xu; Jianing Han; Xinyuan Wang 007; Xinyu Wang; Qinyu Chen; Yuxiang Fu; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers. - Ruiqi Wu; Hui Chen 015; Guoqiang He; Yuxiang Fu; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation. - Qinyu Chen; Guoqiang He; Xinyuan Wang 007; Jin Xu; Sirui Shen; Hui Chen 015; Yuxiang Fu; Li Li 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation. - Wanyuan Hong; Hui Chen 015; Lianghua Quan; Yuxiang Fu; Li Li 003 (ISCAS, 2023)

A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing. - Yuxiang Fu; Kai Chen; Wenqing Song; Guoqiang He; Sirui Shen; Huizheng Wang; Chuan Zhang 001; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow. - Lingxiao Zhu; Wenjie Fan 004; Chenyang Dai; Shize Zhou; Yongqi Xue; Zhonghai Lu; Li Li 003; Yuxiang Fu (IEEE Des. Test, 2023)

Four-class EEG Classification for Seizure Prediction and Detection Using a Lightweight CNN-LSTM. - Heng Zhang 025; Dan Wang; Jinlun Ji; Xiaohan Xue; Congyi Sun; Xinyu Wang; Qinyu Chen; Yuxiang Fu; Li Li 003 (BioCAS, 2024)

Environmental Sound Classification Based on Multi-channel Features and Hybrid Attention. - Guishan Liu; Shuai Zhou; Zhangjun Peng; Li Li 003 (CISP-BMEI, 2024)

TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based Accelerator. - Xinyi Li; Wenjie Fan 004; Heng Zhang 025; Jinlun Ji; Tong Cheng; Shiping Li; Li Li 003; Yuxiang Fu (ACM Great Lakes Symposium on VLSI, 2024)

Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data. - Wenqing Song; Sirui Shen; Congwei Xu; Yilin Wang; Xinyu Wang; Yuxiang Fu; Li Li 003; Zhonghai Lu (IEEE Access, 2024)

HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators. - Siyue Li; Shize Zhou; Yongqi Xue; Wenjie Fan 004; Tong Cheng; Jinlun Ji; Chenyang Dai; Wenqing Song; Qinyu Chen; Chang Gao 002; Li Li 003; Yuxiang Fu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Communication Synchronization-Aware Arbitration Policy in NoC-Based DNN Accelerators. - Wenjie Fan 004; Siyue Li; Lingxiao Zhu; Zhonghai Lu; Li Li 003; Yuxiang Fu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A General Methodology and Reconfigurable Architecture for Calculating AB-Like Functions in the Complex Field. - Ruiqi Wu; Xinyu Wang; Jie Li; Lili Cao; Guoqiang He; Yuxiang Fu; Li Li 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Automatic Generation and Optimization Framework of NoC-Based Neural Network Accelerator Through Reinforcement Learning. - Yongqi Xue; Jinlun Ji; Xinming Yu; Shize Zhou; Siyue Li; Xinyi Li; Tong Cheng; Shiping Li; Kai Chen; Zhonghai Lu; Li Li 003; Yuxiang Fu (IEEE Trans. Computers, 2024)

Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-Chip. - Tong Cheng; Zirui Xu; Xinyi Li; Li Li 003; Yuxiang Fu (ASP-DAC, 2025)

NAME: NoC-based Accelerators Mapping Exploration for High Performance DNN Inference. - Jinlun Ji; Hengyue Gao; Heng Zhang 025; Yuqi Lu; Kai He; Yulong Song; Wenjie Fan 004; Li Li 003; Yuxiang Fu (ISCAS, 2025)

HengNet: An Ultra-lightweight Model with Two-level Reuse Algorithm for Seizure Detection and Prediction. - Heng Zhang 025; Linxiang Wang; Wenjie Fan 004; Zhenglin Gu; Youbin Luo; Xingjie Zou; Chang Gao 002; Qinyu Chen; Yuxiang Fu; Li Li 003 (ISCAS, 2025)

An Energy Efficient Residual Spiking Neural Network Accelerator With Ternary Spikes. - Congyi Sun; Wenqing Song; Qinyu Chen; Chenyang Dai; Yuxiang Fu; Li Li 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

FAS-NoC: A Real-Time Fused Approximation Scheme Coordinating Communication and Computation for NoC-Based NN Accelerators. - Siyue Li; Chuanzhu Liu; Wenjie Fan 004; Heng Zhang 025; Chenyang Dai; Congyi Sun; Xinyu Wang; Li Li 003; Yuxiang Fu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)