A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. - Li Li 038; Jun Ma 005; Yawei Guo; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. - Jun Ma 005; Yawei Guo; Li Li 038; Yue Wu; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

Energy-efficient sub-threshold level shifter. - Liang Wen; Li Li 038; Haibo Wen; Xiaoyang Zeng (ASICON, 2015)

A 24-bit sigma-delta ADC with configurable chopping scheme. - Li Li 038; Xu Cheng 002; Zhang Zhang 004; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2019)