A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. - Rei-Fu Huang; Li-Ming Denq; Cheng-Wen Wu; Jin-Fu Li 001 (MTDT, 2003)

An SOC Test Integration Platform and Its Industrial Realization. - Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Chih-Yen Lo; Li-Ming Denq; Chih-Tsun Huang; Shin-Wei Hung; Jye-Yuan Lee (ITC, 2004)

A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. - Li-Ming Denq; Rei-Fu Huang; Cheng-Wen Wu; Yeong-Jar Chang; Wen Ching Wu (MTDT, 2004)

An Enhanced SRAM BISR Design with Reduced Timing Penalty. - Li-Ming Denq; Tzu-chiang Wang; Cheng-Wen Wu (ATS, 2006)

A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. - Li-Ming Denq; Cheng-Wen Wu (ATS, 2007)

A prototype of a wireless-based test system. - Jing-Jia Liou; Chih-Tsun Huang; Cheng-Wen Wu; Ching-Cheng Tien; Chi-Hu Wang; Hsi-Pin Ma; Ying-Yen Chen; Yueh-Chih Hsu; Li-Ming Denq; Chien-Jung Chiu; Young-Wey Li; Chieh-Ming Chang (SoCC, 2007)

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. - Chun-Kai Hsu; Li-Ming Denq; Mao-Yin Wang; Jing-Jia Liou; Chih-Tsun Huang; Cheng-Wen Wu (ATS, 2008)

Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. - Li-Ming Denq; Yu-Tsao Hsing; Cheng-Wen Wu (IEEE Des. Test Comput., 2009)

Economic Analysis of the HOY Wireless Test Methodology. - Yu-Tsao Hsing; Li-Ming Denq; Chao-Hsun Chen; Cheng-Wen Wu (IEEE Des. Test Comput., 2010)

SOC Test Architecture and Method for 3-D ICs. - Chih-Yen Lo; Yu-Tsao Hsing; Li-Ming Denq; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. - Chin-Fu Li; Chi-Ying Lee; Chen-Hsing Wang; Shu-Lin Chang; Li-Ming Denq; Chun-Chuan Chi; Hsuan-Jung Hsu; Ming-Yi Chu; Jing-Jia Liou; Shi-Yu Huang; Po-Chiun Huang; Hsi-Pin Ma; et al. (DAC, 2011)

A Memory Built-In Self-Repair Scheme Based on Configurable Spares. - Mincent Lee; Li-Ming Denq; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

3D-IC BISR for stacked memories using cross-die spares. - Chun-Chuan Chi; Yung-Fa Chou; Ding-Ming Kwai; Yu-Ying Hsiao; Cheng-Wen Wu; Yu-Tsao Hsing; Li-Ming Denq; Tsung-Hsiang Lin (VLSI-DAT, 2012)