Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. - Jian-Hsing Lee; Yeh-Jen Huang; Li-Yang Hong; Li-Fan Chen; Yeh-Ning Jou; Shin-Cheng Lin; Walter Wohlmuth; Chih-Cherng Liao; Ching-Ho Li; Shoa-Chang Huang; Ke-Horng Chen (IRPS, 2022)

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (ISSCC, 2022)

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (ISSCC, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power. - Yeh-Jen Huang; Li-Yang Hong; Yeh-Ning Jou; Jian-Hsing Lee (ICCE-Taiwan, 2024)

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (IEEE J. Solid State Circuits, 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2024)