A Method to Design 5-Bit Burst Error Correction Code against the Multiple Bit Upset (MBU) in Memories. - Jia-Qiang Li; Li-Yi Xiao; Liu He; Hao-Tian Wu (ASICON, 2019)

Radiation Hardened Design of Pipeline and Register File in Processor. - Li-Yi Xiao; Yuan-Gang Wang; Zu-Qiang Zhang; Jia-Qiang Li; Jie Li (ASICON, 2019)

Susceptibility Evaluation of 3D Integrated Static Random Access Memory with Through-Silicon Vias (TSVs). - Xue-Bing Cao; Li-Yi Xiao; Rong-Sheng Zhang; Jia-Qiang Li; Hong-Chen Li; Jin-Xiang Wang (ICICDT, 2019)