Methodology for analysis of TSV stress induced transistor variation and circuit performance. - Li Yu 009; Wen-Yao Chang; Kewei Zuo; Jean Wang; Douglas Yu; Duane S. Boning (ISQED, 2012)

An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits. - Li Yu 009; Omar Mysore; Lan Wei; Luca Daniel; Dimitri A. Antoniadis; Ibrahim M. Elfadel; Duane S. Boning (ASP-DAC, 2013)

Statistical modeling with the virtual source MOSFET model. - Li Yu 009; Lan Wei; Dimitri A. Antoniadis; Ibrahim M. Elfadel; Duane S. Boning (DATE, 2013)

Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New Measurements. - Li Yu 009; Sharad Saxena; Christopher Hess; Ibrahim Abe M. Elfadel; Dimitri A. Antoniadis; Duane S. Boning (DAC, 2014)

Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation. - Li Yu 009; Sharad Saxena; Christopher Hess; Ibrahim M. Elfadel; Dimitri A. Antoniadis; Duane S. Boning (DATE, 2014)

Statistical library characterization using belief propagation across multiple technology nodes. - Li Yu 009; Sharad Saxena; Christopher Hess; Ibrahim M. Elfadel; Dimitri A. Antoniadis; Duane S. Boning (DATE, 2015)

Efficient integrated circuit statistical modeling and extraction using a Bayesian inference framework. - Li Yu 009 (2015)

Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection. - Li Yu 009; Sharad Saxena; Christopher Hess; Ibrahim Abe M. Elfadel; Dimitri A. Antoniadis; Duane S. Boning (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)