Li Zhang
Affiliations:- Tsinghua University, Institute of Microelectronics, Beijing, China
According to our database1,
Li Zhang
authored at least 19 papers
between 2010 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
Sci. China Inf. Sci., 2018
An Accurate dB-Linear Programmable-Gain Amplifier with Temperature-Robust Characteristic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 60-GHz 360° 5-Bit Phase Shifter With Constant IL Compensation Followed by a Normal Amplifier With ±1 dB Gain Variation and 0.6-dBm OP<sub>-1dB</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Sci. China Inf. Sci., 2017
2016
J. Commun. Inf. Networks, 2016
A 3.1-4.2 GHz automatic amplitude control loop VCO with constant Kvco and <10mV amplitude variation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 64dB gain 60GHz receiver with 7.1dB noise figure for 802.11ad applications in 90nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 24GHz low power and low phase noise PLL frequency synthesizer with constant KVCO for 60GHz wireless applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A 3.45-4.22 GHz PLL frequency synthesizer with constant loop bandwidth for WLAN applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
2013
A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm<sup>2</sup> Die Size in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm<sup>2</sup> Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Understanding dynamic behavior of mm-wave CML divider with injection-locking concept.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A low-power ESD-protected 24GHz receiver front-end with π-type input matching network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
A Wideband Inductorless LNA With Local Feedback and Noise Cancelling for Low-Power Low-Voltage Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010