On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. - Li Zhang 034; Chris R. Jesshope (Euro-Par Workshops, 2007)

The Verification of the On-Chip COMA Cache Coherence Protocol. - Thuy Duong Vu; Li Zhang 034; Chris R. Jesshope (AMAST, 2008)

A general model of concurrency and its implementation as many-core dynamic RISC processors. - Thomas A. M. Bernard; Kostas Bousias; Liang Guang; Chris R. Jesshope; Mike Lankamp; Michiel W. van Tol; Li Zhang 034 (ICSAMOS, 2008)

Evaluating CMPs and Their Memory Architecture. - Chris R. Jesshope; Mike Lankamp; Li Zhang 034 (ARCS, 2009)

Making multi-cores mainstream - from security to scalability. - Chris R. Jesshope; Michael A. Hicks 001; Mike Lankamp; Raphael 'kena' Poss; Li Zhang 034 (PARCO, 2009)

The implementation of an SVP many-core processor and the evaluation of its memory architecture. - Chris R. Jesshope; Mike Lankamp; Li Zhang 034 (SIGARCH Comput. Archit. News, 2009)