Architectural analysis and instruction-set optimization for design of network protocol processors. - Haiyong Xie 001; Li Zhao 002; Laxmi N. Bhuyan (CODES+ISSS, 2003)

NePSim: A Network Processor Simulator with a Power Evaluation Framework. - Yan Luo 001; Jun Yang 002; Laxmi N. Bhuyan; Li Zhao 002 (IEEE Micro, 2004)

SpliceNP: a TCP splicer using a network processor. - Li Zhao 002; Yan Luo 001; Laxmi N. Bhuyan; Ravi R. Iyer 001 (ANCS, 2005)

Design and Implementation of a Content-Aware Switch Using a Network Processor. - Li Zhao 002; Yan Luo 001; Laxmi N. Bhuyan; Ravishankar R. Iyer 001 (Hot Interconnects, 2005)

Hardware Support for Bulk Data Movement in Server Platforms. - Li Zhao 002; Ravi R. Iyer 001; Srihari Makineni; Laxmi N. Bhuyan; Donald Newell (ICCD, 2005)

Anatomy and Performance of SSL Processing. - Li Zhao 002; Ravi R. Iyer 001; Srihari Makineni; Laxmi N. Bhuyan (ISPASS, 2005)

Receive Side Coalescing for Accelerating TCP/IP Processing. - Srihari Makineni; Ravishankar R. Iyer 001; Partha Sarangam; Donald Newell; Li Zhao 002; Ramesh Illikkal; Jaideep Moses (HiPC, 2006)

Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers. - Ravi R. Iyer 001; Mahesh Bhat; Li Zhao 002; Ramesh Illikkal; Srihari Makineni; Michael Jones; Kumar Shiv; Donald Newell (IISWC, 2006)

A Network Processor-Based, Content-Aware Switch. - Li Zhao 002; Yan Luo 001; Laxmi N. Bhuyan; Ravi R. Iyer 001 (IEEE Micro, 2006)

CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms. - Li Zhao 002; Ravi R. Iyer 001; Ramesh Illikkal; Jaideep Moses; Srihari Makineni; Donald Newell (PACT, 2007)

Constraint-Aware Large-Scale CMP Cache Design. - Li Zhao 002; Ravi R. Iyer 001; Srihari Makineni; Ramesh Illikkal; Jaideep Moses; Donald Newell (HiPC, 2007)

Exploring DRAM cache architectures for CMP server platforms. - Li Zhao 002; Ravi R. Iyer 001; Ramesh Illikkal; Donald Newell (ICCD, 2007)

Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance. - Seongbeom Kim; Fang Liu; Yan Solihin; Ravi R. Iyer 001; Li Zhao 002; W. Cohen (ISPASS, 2007)

A Framework for Providing Quality of Service in Chip Multi-Processors. - Fei Guo; Yan Solihin; Li Zhao 002; Ravishankar R. Iyer 001 (MICRO, 2007)

QoS policies and architecture for cache/memory in CMP platforms. - Ravi R. Iyer 001; Li Zhao 002; Fei Guo; Ramesh Illikkal; Srihari Makineni; Donald Newell; Yan Solihin; Lisa R. Hsu; Steven K. Reinhardt (SIGMETRICS, 2007)

Exploring Large-Scale CMP Architectures Using ManySim. - Li Zhao 002; Ravi R. Iyer 001; Jaideep Moses; Ramesh Illikkal; Srihari Makineni; Donald Newell (IEEE Micro, 2007)

From chaos to QoS: case studies in CMP resource management. - Fei Guo; Hari Kannan; Li Zhao 002; Ramesh Illikkal; Ravi R. Iyer 001; Don Newell; Yan Solihin; Christos Kozyrakis (SIGARCH Comput. Archit. News, 2007)

Hardware Support for Accelerating Data Movement in Server Platform. - Li Zhao 002; Laxmi N. Bhuyan; Ravi R. Iyer 001; Srihari Makineni; Donald Newell (IEEE Trans. Computers, 2007)

Towards hybrid last level caches for chip-multiprocessors. - Li Zhao 002; Ravi R. Iyer 001; Mike Upton; Don Newell (SIGARCH Comput. Archit. News, 2008)

Architecture Support for Improving Bulk Memory Copying and Initialization Performance. - Xiaowei Jiang; Yan Solihin; Li Zhao 002; Ravishankar R. Iyer 001 (PACT, 2009)

Frequent value compression in packet-based NoC architectures. - Ping Zhou; Bo Zhao 007; Yu Du 002; Yi Xu 010; Youtao Zhang; Jun Yang 002; Li Zhao 002 (ASP-DAC, 2009)

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. - Niti Madan; Li Zhao 002; Naveen Muralimanohar; Aniruddha N. Udipi; Rajeev Balasubramonian; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell (HPCA, 2009)

Hardware/Software Co-Simulation for Last Level Cache Exploration. - Tao Wang 004; Qigang Wang; Dong Liu; Michael Liao; Kevin Wang; Lu Cao; Li Zhao 002; Ravi R. Iyer 001; Ramesh Illikkal; John Du; Liang Wang (NAS, 2009)

VM3: Measuring, modeling and managing VM shared resources. - Ravi R. Iyer 001; Ramesh Illikkal; Omesh Tickoo; Li Zhao 002; Padma Apparao; Don Newell (Comput. Networks, 2009)

Virtual platform architectures for resource metering in datacenters. - Ravi R. Iyer 001; Ramesh Illikkal; Li Zhao 002; Don Newell; Jaideep Moses (SIGMETRICS Perform. Evaluation Rev., 2009)

NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies. - Li Zhao 002; Ravi R. Iyer 001; Srihari Makineni; Don Newell; Liqun Cheng (Conf. Computing Frontiers, 2010)

CHOP: Adaptive filter-based DRAM caching for CMP server platforms. - Xiaowei Jiang; Niti Madan; Li Zhao 002; Mike Upton; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell; Yan Solihin; Rajeev Balasubramonian (HPCA, 2010)

Performance characterization and acceleration of Optical Character Recognition on handheld platforms. - Sadagopan Srinivasan; Li Zhao 002; Lin Sun; Zhen Fang 002; Peng Li 031; Tao Wang 004; Ravishankar R. Iyer 001; Dong Liu (IISWC, 2010)

Quality of service shared cache management in chip multiprocessor architecture. - Fei Guo; Yan Solihin; Li Zhao 002; Ravishankar R. Iyer 001 (ACM Trans. Archit. Code Optim., 2010)

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. - Carlos Flores Fajardo; Zhen Fang 002; Ravi R. Iyer 001; German Fabila Garcia; Seung Eun Lee; Li Zhao 002 (DAC, 2011)

ACCESS: Smart scheduling for asymmetric cache CMPs. - Xiaowei Jiang; Asit K. Mishra; Li Zhao 002; Ravishankar R. Iyer 001; Zhen Fang 002; Sadagopan Srinivasan; Srihari Makineni; Paul Brett; Chita R. Das (HPCA, 2011)

Cost-effectively offering private buffers in SoCs and CMPs. - Zhen Fang 002; Li Zhao 002; Ravishankar R. Iyer 001; Carlos Flores Fajardo; German Fabila Garcia; Seung Eun Lee; Bin Li 018; Steve R. King; Xiaowei Jiang; Srihari Makineni (ICS, 2011)

HeteroScouts: hardware assist for OS scheduling in heterogeneous CMPs. - Sadagopan Srinivasan; Ravishankar R. Iyer 001; Li Zhao 002; Ramesh Illikkal (SIGMETRICS, 2011)

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs. - Bin Li 018; Li Zhao 002; Ravi R. Iyer 001; Li-Shiuan Peh; Michael Leddige; Michael Espig; Seung Eun Lee; Donald Newell (J. Parallel Distributed Comput., 2011)

CHOP: Integrating DRAM Caches for CMP Server Platforms. - Xiaowei Jiang; Niti Madan; Li Zhao 002; Mike Upton; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell; Yan Solihin; Rajeev Balasubramonian (IEEE Micro, 2011)

Efficient interaction between OS and architecture in heterogeneous platforms. - Sadagopan Srinivasan; Li Zhao 002; Ramesh Illikkal; Ravishankar R. Iyer 001 (ACM SIGOPS Oper. Syst. Rev., 2011)

Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System. - Bin Li 018; Zhen Fang 002; Li Zhao 002; Xiaowei Jiang; Lin Li; Andrew Herdrich; Ravishankar R. Iyer 001; Srihari Makineni (Euro-Par, 2012)

QuickIA: Exploring heterogeneous architectures on real prototypes. - Nagabhushan Chitlur; Ganapati Srinivasa; Scott Hahn; P. K. Gupta; Dheeraj Reddy; David A. Koufaty; Paul Brett; Abirami Prabhakaran; Li Zhao 002; Nelson Ijih; Suchit Subhaschandra; Sabina Grover; et al. (HPCA, 2012)

Reducing L1 caches power by exploiting software semantics. - Zhen Fang 002; Li Zhao 002; Xiaowei Jiang; Shih-Lien Lu; Ravi R. Iyer 001; Tong Li 003; Seung Eun Lee (ISLPED, 2012)

Dynamic QoS management for chip multiprocessors. - Bin Li 018; Li-Shiuan Peh; Li Zhao 002; Ravi R. Iyer 001 (ACM Trans. Archit. Code Optim., 2012)

EMERALD: Characterization of emerging applications and algorithms for low-power devices. - Chuanjun Zhang; Glenn G. Ko; Jungwook Choi; Shang-nien Tsai; Minje Kim; Abner Guzmán-Rivera; Rob A. Rutenbar; Paris Smaragdis; Mi Sun Park; Vijaykrishnan Narayanan; Hongyi Xin; Onur Mutlu; et al. (ISPASS, 2013)

Reducing cache and TLB power by exploiting memory region and privilege level semantics. - Zhen Fang 002; Li Zhao 002; Xiaowei Jiang; Shih-Lien Lu; Ravi R. Iyer 001; Tong Li 003; Seung Eun Lee (J. Syst. Archit., 2013)

QoS management on heterogeneous architecture for parallel applications. - Ying Zhang 016; Li Zhao 002; Ramesh Illikkal; Ravi R. Iyer 001; Andrew Herdrich; Lu Peng 001 (ICCD, 2014)

POSTER: Intrusion Detection System for In-vehicle Networks using Sensor Correlation and Integration. - Huaxin Li; Li Zhao 002; Marcio Juliato; Shabbir Ahmed; Manoj R. Sastry; Lily L. Yang (CCS, 2017)

Lightweight Block Cipher Circuits for Automotive and IoT Sensor Devices. - Santosh Ghosh; Rafael Misoczki; Li Zhao 002; Manoj R. Sastry (HASP@ISCA, 2017)

QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications. - Ying Zhang 016; Li Zhao 002; Ramesh Illikkal; Ravi R. Iyer 001; Andrew Herdrich; Lu Peng 001 (IEEE Syst. J., 2017)

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)

Cache Compression with Efficient in-SRAM Data Comparison. - Xiaowei Wang; Charles Augustine; Eriko Nurvitadhi; Ravi R. Iyer 001; Li Zhao 002; Reetuparna Das (NAS, 2021)