A coordinated tiling and batching framework for efficient GEMM on GPUs. - Xiuhong Li; Yun Liang 001; Shengen Yan; Liancheng Jia; Yinghan Li (PPoPP, 2019)

Generating Systolic Array Accelerators With Reusable Blocks. - Liancheng Jia; Liqiang Lu; Xuechao Wei; Yun Liang 001 (IEEE Micro, 2020)

Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels. - Liancheng Jia; Yun Liang 001; Xiuhong Li; Liqiang Lu; Shengen Yan (IEEE Trans. Computers, 2020)

TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. - Liancheng Jia; Zizhang Luo; Liqiang Lu; Yun Liang 001 (DAC, 2021)

TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. - Liqiang Lu; Naiqing Guan; Yuyue Wang 001; Liancheng Jia; Zizhang Luo; Jieming Yin; Jason Cong; Yun Liang 001 (ISCA, 2021)

Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs. - Liancheng Jia; Zizhang Luo; Liqiang Lu; Yun Liang 001 (ISVLSI, 2021)

EMS: efficient memory subsystem synthesis for spatial accelerators. - Liancheng Jia; Yuyue Wang 001; Jingwen Leng; Yun Liang 001 (DAC, 2022)

Downscaling and Overflow-aware Model Compression for Efficient Vision Processors. - Haokun Li; Jing Liu 048; Liancheng Jia; Yun Liang 001; Yaowei Wang 001; Mingkui Tan (ICDCS Workshops, 2022)

Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs. - Zizhang Luo; Liqiang Lu; Yicheng Jin; Liancheng Jia; Yun Liang 001 (FPL, 2023)

TileFlow: A Framework for Modeling Fusion Dataflow via Tree-based Analysis. - Size Zheng 001; Siyuan Chen 007; Siyuan Gao; Liancheng Jia; Guangyu Sun 003; Runsheng Wang; Yun Liang 001 (MICRO, 2023)

Automatic Generation of Spatial Accelerator for Tensor Algebra. - Liancheng Jia; Zizhang Luo; Liqiang Lu; Yun Liang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)