Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. - Pei-Wen Luo; Jwu-E Chen; Chin-Long Wey; Liang-Chia Cheng; Ji-Jan Chen; Wen Ching Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. - Tao Wang; Pei-Wen Luo; Yu-Shih Su; Liang-Chia Cheng; Ding-Ming Kwai; Yiyu Shi 001 (ASP-DAC, 2012)

Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs). - Pei-Wen Luo; Tao Wang; Chin-Long Wey; Liang-Chia Cheng; Bih-Lan Sheu; Yiyu Shi 001 (ISVLSI, 2012)

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. - Bing-Chuan Bai; Chun-Lung Hsu; Ming-Hsueh Wu; Chen-An Chen; Yee-Wen Chen; Kun-Lun Luo; Liang-Chia Cheng; James Chien-Mo Li (Asian Test Symposium, 2013)

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. - Chen-An Chen; Yee-Wen Chen; Chun-Lung Hsu; Ming-Hsueh Wu; Kun-Lun Luo; Bing-Chuan Bai; Liang-Chia Cheng (Asian Test Symposium, 2013)

Benchmarking for research in power delivery networks of three-dimensional integrated circuits. - Pei-Wen Luo; Chun Zhang; Yung-Tai Chang; Liang-Chia Cheng; Hung-Hsie Lee; Bih-Lan Sheu; Yu-Shih Su; Ding-Ming Kwai; Yiyu Shi 001 (ISPD, 2013)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. - Shu-Han Wei; Yu-Min Lee; Chia-Tung Ho; Chih-Ting Sun; Liang-Chia Cheng (VLSI-DAT, 2013)

Variation aware optimal threshold voltage computation for on-chip noise sensors. - Tao Wang; Chun Zhang; Jinjun Xiong; Pei-Wen Luo; Liang-Chia Cheng; Yiyu Shi 001 (ICCAD, 2014)

Incremental transient simulation of power grid. - Chia-Tung Ho; Yu-Min Lee; Shu-Han Wei; Liang-Chia Cheng (ISPD, 2014)

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. - Jyu-Yuan Lai; Chih-Tsun Huang; Ting-Shuo Hsu; Jing-Jia Liou; Tung-Hua Yeh; Liang-Chia Cheng; Juin-Ming Lu (SoCC, 2014)

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. - Shien-Chun Luo; Kuo-Chiang Chang; Ming-Pin Chen; Ching-Ji Huang; Yi-Fang Chiu; Po-Hsun Chen; Liang-Chia Cheng; Chih-Wei Liu; Yuan-Hua Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach. - Hui Geng; Jianming Liu 001; Pei-Wen Luo; Liang-Chia Cheng; Steven L. Grant; Yiyu Shi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling. - Hui Geng; Jianming Liu 001; Jinglan Liu; Pei-Wen Luo; Liang-Chia Cheng; Steven L. Grant; Yiyu Shi 001 (Integr., 2016)

On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors. - Tao Wang; Chun Zhang; Jinjun Xiong; Pei-Wen Luo; Liang-Chia Cheng; Yiyu Shi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Thermal modeling and design on smartphones with heat pipe cooling technique. - Hong-Wen Chiou; Yu-Min Lee; Hsuan-Hsuan Hsiao; Liang-Chia Cheng (ICCAD, 2017)

Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. - Chung-Han Chou; Yenting Lai; Yi-Chun Chang; Chih-Yu Wang 002; Liang-Chia Cheng; Shih-Hsu Huang; Shih-Chieh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)