A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. - Min-Han Hsieh; Liang-Hsin Chen; Shen-Iuan Liu; Charlie Chung-Ping Chen (ISSCC, 2012)

A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. - Min-Han Hsieh; Liang-Hsin Chen; Shen-Iuan Liu; Charlie Chung-Ping Chen (IEEE J. Solid State Circuits, 2016)