A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing. - Liang-Hsin Lin; Zih-Sing Fu; Po-Shao Chen; Bo-Yin Yang; Chia-Hsiang Yang (VLSI Technology and Circuits, 2023)

An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices. - Sheng-Jung Yu; Yu-Chi Lee; Liang-Hsin Lin; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2023)

17.3 A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation. - Liang-Hsin Lin; Yao-Kai Yang; Chia-Hsiang Yang (ISSCC, 2025)