A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. - Liang Qi 002; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch. - Yanquan Luo; Liang Qi 002; Ankesh Jain; Maurits Ortmanns (ISCAS, 2018)

Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. - Liang Qi 002; Sai-Weng Sin; Rui Paulo Martins (ASICON, 2019)

A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (ISSCC, 2019)

A Self-coupled DT MASH ΔΣ Modulator with High Tolerance to Noise Leakage. - Gaofeng Tan; Haolin Lu; Xinyu Qin; Jiliang Zhang 009; Jingying Zhang; Yan Liu 016; Liang Qi 002 (APCCAS, 2020)

A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. - Dongyang Jiang; Liang Qi 002; Sai-Weng Sin; Franco Maloberti; Rui Paulo Martins (VLSI Circuits, 2020)

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (IEEE J. Solid State Circuits, 2020)

A Generic Nano-Watt Power Fully Tunable 1-D Gaussian Kernel Circuit for Artificial Neural Network. - Ahmed Reda Mohamed; Liang Qi 002; Yongfu Li 002; Guoxing Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Advances in Continuous-time MASH ΔΣ Modulators. - Liang Qi 002; Xinyu Qin; Sai-Weng Sin; Chixiao Chen; Fan Ye 001; Guoyong Shi; Guoxing Wang (ASICON, 2021)

Low-Hardware-Cost SNN employing FeFET-based Neurons with Tunable Leaky Effect. - Hongyi Liu 007; Xiangao Qi; Yuqing Lou; Liang Qi 002; Zuo-Wei Yeh; Kea-Tiong Tang; Jian Zhao 004 (BioCAS, 2021)

An Adaptively-controlled High-efficiency Buck Converter with Wide Dynamic Range for IoT Applications. - Zhuo Gao; Mingyi Chen; Liang Qi 002; Yongfu Li 002; Jun Yan (ICTA, 2021)

A 10-Mbps 119.2-pJ/bit Software Defined Body Channel Transceiver Employing a CCII-based PGA and a 2.5-bit/cycle ADC in 180-nm CMOS. - Tao He; Zhen Kong; Xu Liang; Jing Luo; Longyang Lin; Liang Qi 002; Yongfu Li 002; Jian Zhao 004; Guoxing Wang (ICTA, 2021)

Discrete-Time MASH Delta-Sigma Modulator with an IIR-based Self-Coupling. - Yue Hu; Jingying Zhang; Yang Zhao; Mingyi Chen; Liang Qi 002 (ICTA, 2021)

A Multi-Rate Hybrid DT/CT Mash ΔΣ Modulator with High Tolerance to Noise Leakage. - Jiliang Zhang 009; Gaofeng Tan; Yue Hu; Jian Zhao 004; Mingyi Chen; Yongfu Li 002; Liang Qi 002 (ISCAS, 2021)

A 1-μA-Quiescent-Current Capacitor-Less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit. - Weifu Chen; Mingyi Chen; Yuzhi Hao; Liang Qi 002; Jian Zhao 004 (ISCAS, 2021)

An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V. - Ce Ma; Yuxin Ji; Cai Qiao; Ting Zhou; Liang Qi 002; Yongfu Li 002 (ISCAS, 2021)

Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. - Xinyu Qin; Jingying Zhang; Liang Qi 002; Sai-Weng Sin; Rui Paulo Martins; Guoxing Wang (ISCAS, 2021)

Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review. - Mingyi Chen; Yuzhi Hao; Liang Qi 002; Yongfu Li 002; Jun Yan (ISOCC, 2021)

Continuous-time Delta-Sigma Modulators: Single-loop versus MASH. - Liang Qi 002; Tianming Ni; Xinyu Qin; Mingyi Chen; Yongfu Li 002; Guoxing Wang (ISOCC, 2021)

Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. - Danfeng Zhai; Chixiao Chen; Liang Qi 002; Fan Ye 001; Junyan Ren (ISOCC, 2021)

Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. - Jingying Zhang; Yang Zhao; Mingyi Chen; Chixiao Chen; Fan Ye 001; Liang Qi 002 (ISOCC, 2021)

An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique. - Chao Wang 101; Yuxin Ji; Ce Ma; Qiao Cai; Liang Qi 002; Yongfu Li 002 (IEEE Access, 2021)

A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation. - Dongyang Jiang; Liang Qi 002; Sai-Weng Sin; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A power-efficient and re-configurable analog artificial neural network classifier. - Ahmed Reda Mohamed; Liang Qi 002; Guoxing Wang (Microelectron. J., 2021)

A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. - Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Gang Xiao 001; Rui Paulo Martins (CICC, 2022)

A Sub-0.01° Phase Resolution 6.8-mW fNIRS Readout Circuit Employing a Mixer-First Frequency-Domain Architecture. - Cheng Chen; Zhouchen Ma; Yaxin Liu; Zhenhong Liu; Linfeng Zhou; Yan Wu; Liang Qi 002; Yongfu Li 002; Mohamad Sawan; Guoxing Wang; Jian Zhao 004 (ESSCIRC, 2022)

A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. - Ke Li; Sai-Weng Sin; Liang Qi 002; Weibing Zhao; Guoxing Wang; Rui Paulo Martins (ISCAS, 2022)

A 124 dB dynamic range sigma-delta modulator applied to non-invasive EEG acquisition using chopper-modulated input-scaling-down technique. - Kaiquan Chen; Mingyi Chen; Longlong Cheng; Liang Qi 002; Guoxing Wang; Yong Lian 001 (Sci. China Inf. Sci., 2022)

Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. - Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Dengke Xu; Guoxing Wang; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Hybrid 1st/2nd-Order VCO-Based CTDSM With Rail-to-Rail Artifact Tolerance for Bidirectional Neural Interface. - Huaiyu Liu; Tongtong Guo; Peng Yan; Liang Qi 002; Mingyi Chen; Guoxing Wang; Yan Liu 016 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A VCO-Based CTDSM With Integrated Phase Error Correction for Neural Interface. - Huaiyu Liu; Liang Qi 002; Guoxing Wang; Yan Liu 016 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. - Liang Qi 002; Yuekai Liu; Sai-Weng Sin; Xinpeng Xing; Guoxing Wang; Maurits Ortmanns; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Low-Noise, High-Linearity Sine-Wave Generation Using Noise-Shaping Phase-Switching Technique. - Jiajie Huang; Ting Zhou; Huaiyu Liu; Liang Qi 002; Yan Liu 016; Yongfu Li 002 (IEEE Trans. Instrum. Meas., 2022)

A CT DSM with DAC Scaling Technique for Direct Neural Recording Front-End. - Yuekai Liu; Jinlei Pan; Liang Qi 002 (ASICON, 2023)

Weightings in Incremental ADCs: A Tutorial Review. - Ruiqi Gao; Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Biao Wang; Guoxing Wang; Rui Paulo Martins (CICC, 2023)

A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting. - Yuhan Pan; Qingxun Wang; Kaiquan Chen; Bin Cai; Jiuchao Qian; Yong Lian 001; Liang Qi 002 (ISCAS, 2023)

A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling. - Qingxun Wang; Yuhan Pan; Kaiquan Chen; Yu Lin; Biao Wang; Liang Qi 002 (ISCAS, 2023)

CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition. - Jieyu Li; Weifeng He; Bo Zhang 105; Liang Qi 002; Guanghui He; Mingoo Seok (ISSCC, 2023)

A Zoom Architecture Using Linear-Exponential Incremental ADC. - Qingxun Wang; Kaiquan Chen; Liang Qi 002 (NEWCAS, 2023)

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. - Jingying Zhang; Sai-Weng Sin; Yan Liu 016; Fan Ye 001; Guoxing Wang; Maurits Ortmanns; Liang Qi 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery. - Huaiyu Liu; Yang Lin; Liang Qi 002; Yongwei Lou; Guoxing Wang; Yan Liu 016 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. - Kaiquan Chen; Biao Wang; Yan Liu 016; Fan Ye 001; Sai-Weng Sin; Guoxing Wang; Yong Lian 001; Liang Qi 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. - Shulin Zhao 004; Mingqiang Guo; Liang Qi 002; Dengke Xu; Guoxing Wang; Rui Paulo Martins; Sai-Weng Sin (IEEE J. Solid State Circuits, 2023)

A Re-Configurable Body Channel Transceiver Towards Wearable and Flexible Biomedical Sensor Networks. - Tao He; Jing Luo; Zhen Kong; Xu Liang; Longyang Lin; Bo Zhao 003; Liang Qi 002; Yongfu Li 002; Guoxing Wang; Jian Zhao 004 (IEEE Trans. Biomed. Circuits Syst., 2023)

A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. - Mingqiang Guo; Liang Qi 002; Weibing Zhao; Gang Xiao 001; Rui Paulo Martins; Sai-Weng Sin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator. - Yue Hu; Yuekai Liu; Xinyu Qin; Yan Liu 016; Mingqiang Guo; Sai-Weng Sin; Guoxing Wang; Yong Lian 001; Liang Qi 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. - Gaofeng Tan; Xinyu Qin; Yan Liu 016; Mingqiang Guo; Sai-Weng Sin; Guoxing Wang; Yong Lian 001; Liang Qi 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 5.76GS/s 180MHz-BW 74.1dB-DR 2x TI Extrapolated CT DSM with Broadband Hybrid-Inputs Current-Mode Adder in 28nm CMOS. - Yuekai Liu; Meng Guo; Yichen Jin; Yan Liu 016; Mingqiang Guo; Sai-Weng Sin; Zhichao Tan; Liang Qi 002 (A-SSCC, 2024)

A TFT-Based Flexible PPG Acquisition Circuit in a 3-μm LTPS Process for Packaging-Free Smart Ring Applications. - Hanbo Zhang; Yuqing Lou; Yang Bo; Zhouchen Ma; Hao Wu 007; Liang Qi 002; Yongfu Li 002; Xiaojun Guo; Guoxing Wang; Jian Zhao 004 (A-SSCC, 2024)

A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. - Ke Li; Xianyu Congzhou; Liang Qi 002; Mingqiang Guo; Rui Paulo Martins; Sai-Weng Sin (CICC, 2024)

A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS. - Xinyu Qin; Yichen Jin; Guoxing Wang; Sai-Weng Sin; Maurits Ortmanns; Yong Lian 001; Liang Qi 002 (CICC, 2024)

Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing. - Ran Zhang; Ka-Fai Un; Zhensheng Li; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (ICTA, 2024)

Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM. - Meng Guo; Yuekai Liu; Jinlei Pan; Liang Qi 002 (ISCAS, 2024)

A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. - Ran Zhang; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Dengke Xu; Weibing Zhao; Rui Paulo Martins; Franco Maloberti; Sai-Weng Sin (ISCAS, 2024)

An Energy-Efficient FD-fNIRS Readout Circuit Employing a Mixer-First Analog Frontend and a $ Sigma$-$ Delta$ Phase-to-Digital Converter. - Zhouchen Ma; Cheng Chen; Yuxiang Lin; Liang Qi 002; Yongfu Li 002; Xia Bi; Mohamad Sawan; Guoxing Wang; Jian Zhao 004 (IEEE Trans. Biomed. Circuits Syst., 2024)

A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification. - Haoyu Li; Boyang Wang; Hongjiang Chen; Sai-Weng Sin; Yutao Peng; Xizhu Peng; He Tang; Chao Fan; Liang Qi 002; Rui Paulo Martins; Mingqiang Guo (CICC, 2025)

A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering. - Ke Li; Haoyu Gong; Xianyu Congzhou; Zhensheng Li; Liang Qi 002; Mingqiang Guo; Rui Paulo Martins; Sai-Weng Sin (IEEE J. Solid State Circuits, 2025)

A 394-TOPS/W Matched Filter With Charge-Domain Computing for GPS Signal Acquisition. - Jieyu Li; Weifeng He; Bo Zhang 105; Chuxiong Lin; Liang Qi 002; Dingxuan Liu; Mingoo Seok (IEEE J. Solid State Circuits, 2025)

A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation. - Ran Zhang; Xueru Cen; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)