Low overhead task migration mechanism in NoC-based MPSoC. - Fangfa Fu; Liang Wang 020; Yu Lu; Jinxiang Wang 001 (ASICON, 2013)

Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip. - Liang Wang 020; Xiaohang Wang 001; Terrence S. T. Mak (VLSI-SoC, 2014)

Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip. - Liang Wang 020; Xiaohang Wang 001; Terrence S. T. Mak (VLSI-SoC (Selected Papers), 2014)

SlideAcross: A Low-Latency Adaptive Router for Chip Multi-processor. - Wen Zong; Liang Wang 020; Qiang Xu 001; Michael Opoku Agyeman (DSD, 2016)

Adaptive Routing Algorithms for Lifetime Reliability Optimization in Network-on-Chip. - Liang Wang 020; Xiaohang Wang 001; Terrence S. T. Mak (IEEE Trans. Computers, 2016)

Runtime task mapping for lifetime budgeting in many-core systems. - Liang Wang 020; Xiaohang Wang 001; Ho-fung Leung; Terrence S. T. Mak (FDL, 2017)

Throughput Optimization for Lifetime Budgeting in Many-Core Systems. - Liang Wang 020; Xiaohang Wang 001; Ho-fung Leung; Terrence S. T. Mak (ACM Great Lakes Symposium on VLSI, 2017)

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. - Liang Wang 020; Ping Lv; Leibo Liu; Jie Han 001; Ho-fung Leung; Xiaohang Wang 001; Shouyi Yin; Shaojun Wei; Terrence S. T. Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs. - Liang Wang 020; Xiaohang Wang 001; Ho-fung Leung; Terrence S. T. Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology. - Liang Wang 020; Leibo Liu; Xiaohang Wang 001; Jie Han 001; Chenchen Deng; Shaojun Wei (DAC, 2020)

On hardware-trojan-assisted power budgeting system attack targeting many core systems. - Yiming Zhao; Xiaohang Wang 001; Yingtao Jiang; Liang Wang 020; Mei Yang 001; Amit Kumar Singh 002; Terrence S. T. Mak (J. Syst. Archit., 2020)

Aggressive Fine-Grained Power Gating of NoC Buffers. - Yibo Wu; Leibo Liu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Chenchen Deng; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings. - Liang Wang 020; Leibo Liu; Jie Han 001; Xiaohang Wang 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2020)

UPM-DMA: An Efficient Userspace DMA-Pinned Memory Management Strategy for NVMe SSDs. - Jinbin Zhu; Limin Xiao; Liang Wang 020; Guangjun Qin; Rui Zhang; Yuting Liu; Zhonglin Liu (ICA3PP (1), 2021)

An enhanced planned obsolescence attack by aging networks-on-chip. - Yinyuan Zhao; Xiaohang Wang 001; Yingtao Jiang; Liang Wang 020; Amit Kumar Singh 002; Letian Huang; Mei Yang 001 (J. Syst. Archit., 2021)

On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. - Siyuan Xiao; Xiaohang Wang 001; Maurizio Palesi; Amit Kumar Singh 002; Liang Wang 020; Terrence S. T. Mak (IEEE Trans. Computers, 2021)

A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs. - Yibo Wu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. - Yibo Wu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Jianfeng Zhu 001; Honglan Jiang; Shouyi Yin; Shaojun Wei; Leibo Liu (HPCA, 2022)

SWin: A Set-Window Division Mechanism to Alleviate I/O Jitters of NVMe SSD Drives. - Yuting Liu; Liang Wang 020; Jinbin Zhu; Runnan Shen; Shixuan Jiang; Limin Xiao (HPCC/DSS/SmartCity/DependSys, 2022)

Hypergraph-partitioning-based online joint scheduling of tasks and data. - Yao Song; Liang Wang 020; Limin Xiao; Wei Wei 006; Rafal Scherer; Guangjun Qin; Jinquan Wang (J. Supercomput., 2022)

Shogun: A Task Scheduling Framework for Graph Mining Accelerators. - Yibo Wu; Jianfeng Zhu 001; Wenrui Wei; Longlong Chen; Liang Wang 020; Shaojun Wei; Leibo Liu (ISCA, 2023)

ReDas: Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array. - Meng Han; Liang Wang 020; Limin Xiao; Tianhao Cai; Zeyu Wang; Xiangrong Xu; Chenhao Zhang (CoRR, 2023)

ATA-Cache: Contention Mitigation for GPU Shared L1 Cache with Aggregated Tag Array. - Xiangrong Xu; Liang Wang 020; Limin Xiao; Lei Liu 037; Xilong Xie; Meng Han; Hao Liu (CoRR, 2023)

CFIO: A conflict-free I/O mechanism to fully exploit internal parallelism for Open-Channel SSDs. - Jinbin Zhu; Liang Wang 020; Limin Xiao; Lei Liu 037; Guangjun Qin (J. Syst. Archit., 2023)

Dynamic two-side matching of tasks and resources in wide-area distributed computing environments. - Yao Song; Liang Wang 020; Limin Xiao; Runnan Shen; Jinquan Wang; Chenhao Zhang (J. Supercomput., 2023)

QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds. - Meng Han; Liang Wang 020; Limin Xiao; Hao Zhang; Chenhao Zhang; Xiangrong Xu; Jianfeng Zhu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

EBIO: An Efficient Block I/O Stack for NVMe SSDs With Mixed Workloads. - Jinbin Zhu; Liang Wang 020; Limin Xiao; Lei Liu 037; Guangjun Qin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

BitNN: A Bit-Serial Accelerator for K-Nearest Neighbor Search in Point Clouds. - Meng Han; Liang Wang 020; Limin Xiao; Hao Zhang; Tianhao Cai; Jiale Xu; Yibo Wu; Chenhao Zhang; Xiangrong Xu (ISCA, 2024)

ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array. - Xiangrong Xu; Liang Wang 020; Limin Xiao; Lei Liu 037; Yuanqiu Lv; Xilong Xie; Meng Han; Hao Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array. - Meng Han; Liang Wang 020; Limin Xiao; Tianhao Cai; Zeyu Wang; Xiangrong Xu; Chenhao Zhang (IEEE Trans. Computers, 2024)

Minimizing the cost of periodically replicated systems via model and quantitative analysis. - Chenhao Zhang; Liang Wang 020; Limin Xiao; Shixuan Jiang; Meng Han; Jinquan Wang; Bing Wei; Guangjun Qin (Frontiers Comput. Sci., 2024)

FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs. - Xilong Xie; Liang Wang 020; Limin Xiao; Meng Han; Lin Sun; Shuai Zheng; Xiangrong Xu (DATE, 2025)

Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache. - Xiangrong Xu; Liang Wang 020; Limin Xiao; Lei Liu 037; Zihao Zhou; Yuanqiu Lv; Li Ruan; Xilong Xie; Meng Han; Xiaojian Liao (J. Syst. Archit., 2025)