Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. - Liang Zhang 012; Michael S. Hsiao; Indradeep Ghosh (Asian Test Symposium, 2003)

Efficient Sequential ATPG for Functional RTL Circuits. - Liang Zhang 012; Indradeep Ghosh; Michael S. Hsiao (ITC, 2003)

Incremental deductive & inductive reasoning for SAT-based bounded model checking. - Liang Zhang 012; Mukul R. Prasad; Michael S. Hsiao (ICCAD, 2004)

Interleaved Invariant Checking with Dynamic Abstraction. - Liang Zhang 012; Mukul R. Prasad; Michael S. Hsiao (CHARME, 2005)

Dynamic abstraction using SAT-based BMC. - Liang Zhang 012; Mukul R. Prasad; Michael S. Hsiao; Thomas Sidle (DAC, 2005)

Design Verification for Sequential Systems at Various Abstraction Levels. - Liang Zhang 012 (2005)

A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. - Liang Zhang 012; Indradeep Ghosh; Michael S. Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)