Simplified delay design guidelines for on-chip global interconnects. - Liang Zhang 038; Wentai Liu; Rizwan Bashirullah; John M. Wilson 002; Paul D. Franzon (ACM Great Lakes Symposium on VLSI, 2004)

Driver pre-emphasis techniques for on-chip global buses. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (ISLPED, 2005)

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver. - Lei Luo 006; John M. Wilson 002; Stephen E. Mick; Jian Xu; Liang Zhang 038; Evan Erickson; Paul D. Franzon (CICC, 2006)

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (CICC, 2006)

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver. - Lei Luo 006; John M. Wilson 002; Stephen E. Mick; Jian Xu; Liang Zhang 038; Paul D. Franzon (IEEE J. Solid State Circuits, 2006)

Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (IEEE Trans. Very Large Scale Integr. Syst., 2009)