An ADPLL-based fast start-up technique for sensor radio frequency synthesizers. - Liangge Xu; Saska Lindfors; Jussi Ryynänen (ICECS, 2008)

A high-speed variable phase accumulator for an ADPLL architecture. - Liangge Xu; Saska Lindfors (ISCAS, 2008)

Agile frequency synthesizer for cognitive radios. - Liangge Xu; Kari Stadius; Tapio Rapinoja; Jussi Ryynänen (ECCTD, 2009)

A low-power wide-band digital frequency synthesizer for cognitive radio sensor units. - Liangge Xu; Kari Stadius; Jussi Ryynänen (ESSCIRC, 2009)

A wide-band digitally controlled ring oscillator. - Liangge Xu; Kari Stadius; Jussi Ryynänen (ISCAS, 2010)

A 2.4-GHz Low-Power All-Digital Phase-Locked Loop. - Liangge Xu; Saska Lindfors; Kari Stadius; Jussi Ryynänen (IEEE J. Solid State Circuits, 2010)

Implementation of all-digital wideband RF frequency synthesizers in 65-nm CMOS technology. - Tapio Rapinoja; Liangge Xu; Kari Stadius; Jussi Ryynänen (ISCAS, 2011)

An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique. - Liangge Xu; Kari Stadius; Jussi Ryynänen (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)