A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. - Yu Wang 046; Dawei Ye; Liangjian Lyu; Yingfei Xiang; Hao Min; Chuanjin Richard Shi (ISSCC, 2018)

A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. - Liangjian Lyu; Yu Wang 046; Chixiao Chen; Chuanjin Richard Shi (ASP-DAC, 2019)

A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. - Liangjian Lyu; Dawei Ye; Chuanjin Richard Shi (ISCAS, 2019)

A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. - Dawei Ye; Rongjin Xu; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2019)

A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. - Yuting Tu; Rongjin Xu; Dawei Ye; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2020)

A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. - Liangjian Lyu; Yu Wang 046; Chixiao Chen; Chuanjin Richard Shi (Integr., 2020)

A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. - Dawei Ye; Yu Wang 046; Yingfei Xiang; Liangjian Lyu; Hao Min; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2020)

A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. - Liangjian Lyu; Dawei Ye; Chuanjin Richard Shi (IEEE Trans. Biomed. Circuits Syst., 2020)

A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. - Liangjian Lyu; Dawei Ye; Rongjin Xu; Geng Mu; Heng Zhao; Yingfei Xiang; Yuting Tu; Yiyun Zhang; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. - Geng Mu; Dawei Ye; Liangjian Lyu; Xiaobin Zhao; Chuanjin Richard Shi (CICC, 2021)

A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. - Renze Gan; Liangjian Lyu; Geng Mu; Chuanjin Richard Shi (CICC, 2022)

Flexible Pressure Sensor Array with Multi-Channel Wireless Readout Chip. - Haohan Wangxu; Liangjian Lyu; Hengchang Bi; Xing Wu 005 (Sensors, 2022)

A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces. - Qingzhen Wang; Wenxian Gu; Hengchang Bi; Liangjian Lyu; Deli Qiao; Xing Wu 005 (ASICON, 2023)

A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction. - Jingsen Yang; Liangjian Lyu; Zirui Dong; Heyu Ren; Chuanjin Richard Shi (A-SSCC, 2023)

A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF. - Renze Gan; Liangjian Lyu; Chuanjin Richard Shi (ESSCIRC, 2023)

Microscopic Characterization of Failure Mechanisms in Long-Term Implanted Microwire Neural Electrodes. - Zijian Zhang; Q. Li; Zuoyuan Dong; Wanting Wang; S. T. Lai; Xin Yang; Fang Liang; Chaolun Wang; C. Luo; Liangjian Lyu; Z. Li; J. M. Xu; et al. (IRPS, 2023)

A $2.53 mu mathrm{W}/ text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. - Hao Jiang 024; Jiapei Zheng; Yunzhengmao Wang; Jinshan Zhang 006; Haozhe Zhu; Liangjian Lyu; Yingping Chen; Chixiao Chen; Qi Liu 010 (ISCAS, 2023)

A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR. - Heyu Ren; Liangjian Lyu; Binbin Chen; Chuanjin Richard Shi (CICC, 2024)

A 40µW 915MHz Receiver with Sub-Passive Third-Harmonic Mixer Achieving -88dBm Sensitivity and Multi-Channel Selection. - Binbin Chen; Heyu Ren; Wenjun Gong; Sirou Li; Liangjian Lyu; C.-J. Richard Shi (ISCAS, 2025)

A 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity. - Binbin Chen; Heyu Ren; Wenjun Gong; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2025)

A 240-mV 33.8-μV/°C 1.5-nW Voltage Detector for Energy Harvesting. - Wenjun Gong; Binbin Chen; Liangjian Lyu; C.-J. Richard Shi (ISCAS, 2025)

A 0.473 μJ/class Seizure Detection Processor with LSVM Classifier and LPF-Based Feature Extraction. - Wenxian Gu; Xudong Hao; Hengchang Bi; Xing Wu 005; C.-J. Richard Shi; Liangjian Lyu (ISCAS, 2025)

A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N. - Sirou Li; Weijia Zeng; Kaiyun Cao; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2025)

A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity. - Heyu Ren; Liangjian Lyu; Binbin Chen; Wenjun Gong; Xing Wu 005; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2025)