A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis. - Jincai Liu; Weixin Gai; Liangxiao Tang (ISCAS, 2015)

A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier. - Shihao Li; Weixin Gai; Xiao Xiang; Liangxiao Tang; Jichao Huang; Tong Zhao; Xiaoting Zhi (ISCAS, 2016)

PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer. - Liangxiao Tang; Weixin Gai; Linqi Shi (ISCAS, 2016)

A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery. - Liangxiao Tang; Weixin Gai; Linqi Shi; Xiao Xiang (ISCAS, 2017)

A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor. - Linqi Shi; Weixin Gai; Jichao Huang; Liangxiao Tang; Xiao Xiang (ISCAS, 2018)

An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor. - Linqi Shi; Weixin Gai; Xiaoting Zhi; Liangxiao Tang; Xiao Xiang (ISCAS, 2018)

A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. - Liangxiao Tang; Weixin Gai; Linqi Shi; Xiao Xiang; Kai Sheng; Ai He (ISSCC, 2018)

A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. - Liangxiao Tang; Weixin Gai; Chih-Kong Ken Yang; Bingyi Ye; Congcong Chen (ISCAS, 2021)