Power Efficient IP Lookup with Supernode Caching. - Lu Peng 001; Wencheng Lu; Lide Duan (GLOBECOM, 2007)

Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics. - Lide Duan; Bin Li 008; Lu Peng 001 (HPCA, 2009)

Expediating IP lookups with reduced power via TBM and SST supernode caching. - Ying Zhang 016; Lu Peng 001; Wencheng Lu; Lide Duan; Suresh Rai (Comput. Commun., 2010)

Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions. - Bin Li 008; Lide Duan; Lu Peng 001 (IEEE Trans. Computers, 2010)

Two-level soft error vulnerability prediction on SMT/CMP architectures. - Lide Duan; Lu Peng 001; Bin Li 008 (IISWC, 2011)

Universal rules guided design parameter selection for soft error resilient processors. - Lide Duan; Ying Zhang 016; Bin Li 008; Lu Peng 001 (ISPASS, 2011)

Optimal microarchitectural design configuration selection for processor hard-error reliability. - Ying Zhang 016; Lide Duan; Bin Li 008; Lu Peng 001 (ISQED, 2012)

Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing. - Lide Duan; Lu Peng 001; Bin Li 008 (IEEE Trans. Dependable Secur. Comput., 2013)

Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors. - Ying Zhang 016; Lide Duan; Bin Li 008; Lu Peng 001; Sadagopan Srinivasan (ISQED, 2014)

Design configuration selection for hard-error reliable processors via statistical rules. - Ying Zhang 016; Lide Duan; Bin Li 008; Lu Peng 001; Xin Fu (Microprocess. Microsystems, 2014)

Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules. - Lide Duan; Ying Zhang 016; Bin Li 008; Lu Peng 001 (IEEE Trans. Computers, 2014)

Optimizing Cloud Data Center Energy Efficiency via Dynamic Prediction of CPU Idle Intervals. - Lide Duan; Dongyuan Zhan; Justin Hohnerlein (CLOUD, 2015)

Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors. - Ying Zhang 016; Lide Duan; Bin Li 008; Lu Peng 001; Sadagopan Srinivasan (Microprocess. Microsystems, 2015)

Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read. - Lei Jiang 001; Wujie Wen; Danghui Wang; Lide Duan (ASP-DAC, 2016)

Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress. - Armin Haj Aboutalebi; Lide Duan (CASES, 2017)

Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress. - Hao Yan; Ethan C. Ahn; Lide Duan (CASES, 2017)

RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance. - Armin Haj Aboutalebi; Lide Duan (ICCD, 2017)

FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance. - Hao Yan; Lei Jiang 001; Lide Duan; Wei-Ming Lin; Eugene John (ACM Trans. Embed. Comput. Syst., 2017)

CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration. - Hao Yan; Hebin R. Cherian; Ethan C. Ahn; Lide Duan (ICS, 2018)

Efficient Allocation and Heterogeneous Composition of NVM Crossbar Arrays for Deep Learning Acceleration. - Hao Yan; Armin Haj Aboutalebi; Lide Duan (IPCCC, 2018)

Designing and evaluating hybrid storage for high performance cloud computing. - Swanand Mhalagi; Lide Duan; Paul Rad (SysCon, 2018)

Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism. - Bo Mao; Suzhen Wu; Lide Duan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification. - Haoqiang Guo; Lu Peng 001; Jian Zhang 004; Fang Qi; Lide Duan (ASAP, 2019)

CSOD: Context-Sensitive Overflow Detection. - Hongyu Liu 005; Sam Silvestro; Xiaoyin Wang; Lide Duan; Tongping Liu (CGO, 2019)

Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks. - Haoqiang Guo; Lu Peng 001; Jian Zhang 004; Fang Qi; Lide Duan (IGSC, 2019)

Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations. - Armin Haj Aboutalebi; Ethan C. Ahn; Bo Mao; Suzhen Wu; Lide Duan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Computer comparisons in the presence of performance variation. - Samuel Irving; Bin Li 008; Shaoming Chen; Lu Peng 001; Weihua Zhang; Lide Duan (Frontiers Comput. Sci., 2020)

iCELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration. - Hao Yan; Hebin R. Cherian; Ethan C. Ahn; Xuehai Qian; Lide Duan (IEEE Trans. Parallel Distributed Syst., 2020)

184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. - Dimin Niu; Shuangchen Li; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Yijin Guan; Tianchan Guan; Fei Sun; Fei Xue; Lide Duan; Yuanwei Fang; Hongzhong Zheng; et al. (ISSCC, 2022)