A high data-reuse architecture with double-slice processing for full-search block-matching algorithm. - Yeong-Kang Lai; Lien-Fei Chen (ISCAS (2), 2003)

VLSI architecture of the reconfigurable computing engine for digital signal processing applications. - Lien-Fei Chen; Yeong-Kang Lai (ISCAS (2), 2004)

A performance-driven configurable motion estimator for full-search block-matching algorithm. - Yeong-Kang Lai; Lien-Fei Chen (ISCAS (2), 2004)

A novel memoryless AES cipher architecture for networking applications. - Yeong-Kang Lai; Li-Chung Chang; Lien-Fei Chen; Chih-Chung Chou; Chun-Wei Chiu (ISCAS (4), 2004)

Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications. - Lien-Fei Chen; Tai-Lun Huang; Yeong-Kang Lai (ICASSP (5), 2005)

A two-way SIMD-based reconfigurable computing architecture for multimedia applications. - Yeong-Kang Lai; Lien-Fei Chen; Jian-Chou Chen; Chun-Wei Chiu (ISCAS (5), 2005)

Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000. - Lien-Fei Chen; Tai-Lun Huang; Tzau-Min Chou; Yeong-Kang Lai (ICASSP (3), 2006)

A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications. - Yeong-Kang Lai; Lien-Fei Chen; Jian-Chou Chen; Chun-Wei Chiu (IEICE Trans. Electron., 2006)

Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder. - Lien-Fei Chen; Kun-Hsing Li; Chong-Yu Huang; Yeong-Kang Lai (ICME, 2008)

Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm. - Yeong-Kang Lai; Lien-Fei Chen; Tian-En Hsieh; Shien-Yu Huang (ICME, 2008)

A high-speed 2-D transform architecture with unique kernel for multi-standard video applications. - Chong-Yu Huang; Lien-Fei Chen; Yeong-Kang Lai (ISCAS, 2008)

Model-based early termination scheme for H.264/AVC inter prediction. - Lien-Fei Chen; Shin-Ping Yang; Yeong-Kang Lai (ICASSP, 2009)

Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation. - Lien-Fei Chen; Shien-Yu Huang; Chi-Yao Liao; Yeong-Kang Lai (ISCAS, 2009)

A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform. - Yeong-Kang Lai; Lien-Fei Chen; Yui-Chih Shih (IEEE Trans. Consumer Electron., 2009)

A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC. - Yeong-Kang Lai; Lien-Fei Chen; Wei-Che Chiou (IEEE Trans. Consumer Electron., 2010)

Hybrid parallel motion estimation architecture based on fast top-winners search algorithm. - Yeong-Kang Lai; Lien-Fei Chen; Shien-Yu Huang (IEEE Trans. Consumer Electron., 2010)

18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications. - Chi-Cheng Ju; Tsu-Ming Liu; Kun-Bin Lee; Yung-Chang Chang; Han-Liang Chou; Chih-Ming Wang; Tung-Hsing Wu; Hue-Min Lin; Yi-Hsin Huang; Chia-Yun Cheng; Ting-An Lin; Chun-Chia Chen; et al. (ISSCC, 2015)

A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications. - Chi-Cheng Ju; Tsu-Ming Liu; Kun-Bin Lee; Yung-Chang Chang; Han-Liang Chou; Chih-Ming Wang; Tung-Hsing Wu; Hue-Min Lin; Yi-Hsin Huang; Chia-Yun Cheng; Ting-An Lin; Chun-Chia Chen; et al. (IEEE J. Solid State Circuits, 2016)