Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? - Thomas Chiarella; Liesbeth Witters; Abdelkarim Mercha; Christoph Kerner; Rok Dittrich; Michal Rakowski; Claude Ortolland; Lars-Åke Ragnarsson; Bertrand Parvais; An De Keersgieter; Stefan Kubicek; Augusto Redolfi; et al. (ESSCIRC, 2009)

Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (ISCAS, 2011)

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. - Jacopo Franco; Ben Kaczer; Jérôme Mitard; Maria Toledano-Luque; Felice Crupi; Geert Eneman; Ph. J. Rousse; Tibor Grasser; M. Cho; Thomas Kauerauf; Liesbeth Witters; Geert Hellings; et al. (ICICDT, 2012)

Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Beyond-Si materials and devices for more Moore and more than Moore applications. - Nadine Collaert; AliReza Alian; Hiroaki Arimura; Geert Boccardi; Geert Eneman; Jacopo Franco; Tsvetan Ivanov; Dennis Lin; Jérôme Mitard; S. Ramesh; R. Rooyackers; Marc Schaekers; et al. (ICICDT, 2016)

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling. - A. Vandooren; Liesbeth Witters; Jacopo Franco; Arindam Mallik; Bertrand Parvais; Z. Wu; Amey Walke; V. Deshpande; E. Rosseel; Andriy Hikavyy; W. Li; L. Peng; et al. (ICICDT, 2018)

Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET. - Shimpei Yamaguchi; Liesbeth Witters; Jérôme Mitard; Geert Eneman; Geert Hellings; Andriy Hikavyy; Roger Loo; Naoto Horiguchi (Microelectron. Reliab., 2018)

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. - P. Zhao; Liesbeth Witters; Anne Jourdain; Michele Stucchi; Nicolas Jourdan 002; J. W. Maes; H. Bana; C. Zhu; R. Chukka; F. Sebaai; Kevin Vandersmissen; N. Heylen; et al. (VLSI Technology and Circuits, 2024)