DSP data path synthesis for low-power applications. - Lih-Yih Chiou; Khurram Muhammad; Kaushik Roy 001 (ICASSP, 2001)

Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications. - Lih-Yih Chiou; Khurram Muhammad; Kaushik Roy 001 (VLSI Design, 2001)

Leakage control with efficient use of transistor stacks in single threshold CMOS. - Mark C. Johnson; Dinesh Somasekhar; Lih-Yih Chiou; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. - Lih-Yih Chiou; Swarup Bhunia; Kaushik Roy 001 (DATE, 2003)

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. - Yongtao Wang; Hamid Mahmoodi; Lih-Yih Chiou; Hunsoo Choo; Jongsun Park 001; Woopyo Jeong; Kaushik Roy 001 (ICASSP (5), 2004)

Synthesis of application-specific highly efficient multi-mode cores for embedded systems. - Lih-Yih Chiou; Swarup Bhunia; Kaushik Roy 001 (ACM Trans. Embed. Comput. Syst., 2005)

Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. - Yen-Ting Liu; Lih-Yih Chiou; Soon-Jyh Chang (ISCAS, 2006)

A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique. - Meng-Fan Chang; Lih-Yih Chiou; Kuei-Ann Wen (IEEE J. Solid State Circuits, 2006)

Crosstalk-insensitive via-programming ROMs using content-aware design framework. - Meng-Fan Chang; Lih-Yih Chiou; Kuei-Ann Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. - Lih-Yih Chiou; Shien-Chun Luo (ISCAS, 2007)

System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm. - Lih-Yih Chiou; Yi-Siou Chen; Chih-Hsien Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. - Lih-Yih Chiou; Shien-Chun Luo (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing. - Shien-Chun Luo; Lih-Yih Chiou (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. - Yongtao Wang; Hamid Mahmoodi; Lih-Yih Chiou; Hunsoo Choo; Jongsun Park 001; Woopyo Jeong; Kaushik Roy 001 (J. Signal Process. Syst., 2010)

A fast and effective dynamic trace-based method for analyzing architectural performance. - Yi-Siou Chen; Lih-Yih Chiou; Hsun-Hsiang Chang (ASP-DAC, 2011)

Buffer size minimization method considering mix-clock domains and discontinuous data access. - Lih-Yih Chiou; Liang-Ying Lu; Bo-Chi Lin; Alan P. Su (APCCAS, 2012)

Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. - Shien-Chun Luo; Chi-Ray Huang; Lih-Yih Chiou (ISCAS, 2012)

A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. - Lih-Yih Chiou; Chi-Ray Huang; Ming-Hung Wu (ISCAS, 2014)

An ultra-low-power adaptive-body-bias control for subthreshold circuits. - Shien-Chun Luo; Chi-Ray Huang; Lih-Yih Chiou (VLSI-DAT, 2014)

An effective matrix compression method for GPU-accelerated thermal analysis. - Lih-Yih Chiou; Liang-Ying Lu; Chieh-Yu Lin (VLSI-DAT, 2015)

Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture. - Tsai-Kan Chien; Lih-Yih Chiou; Chieh-Wen Cheng; Shyh-Shyuan Sheu; Pei-Hua Wang; Ming-Jinn Tsai; Chih-I Wu (APCCAS, 2016)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. - Liang-Ying Lu; Ching-Yao Chang; Zhao-Hong Chen; Bo-Ting Yeh; Tai-Hua Lu; Peng-Yu Chen; Pin-Hao Tang; Kuen-Jong Lee; Lih-Yih Chiou; Soon-Jyh Chang; Chien-Hung Tsai; Chung-Ho Chen; et al. (ASP-DAC, 2016)

A low store energy and robust ReRAM-based flip-flop for normally off microprocessors. - Tsai-Kan Chien; Lih-Yih Chiou; Yao-Chun Chuang; Shyh-Shyuan Sheu; Heng-Yuan Li; Pei-Hua Wang; Tzu-Kun Ku; Ming-Jinn Tsai; Chih-I Wu (ISCAS, 2016)

Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications. - Tsai-Kan Chien; Lih-Yih Chiou; Shyh-Shyuan Sheu; Jing-Cian Lin; Chang-Chia Lee; Tzu-Kun Ku; Ming-Jinn Tsai; Chih-I Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

A novel clock-pulse-width calibration technique for charge redistribution DACs. - Hugo Cruz; Hong-Yi Huang; Ching-Hsing Luo; Lih-Yih Chiou; Shuenn-Yuh Lee (ISCAS, 2017)

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. - Tsai-Kan Chien; Lih-Yih Chiou; Yi-Sung Tsou; Shyh-Shyuan Sheu; Pei-Hua Wang; Ming-Jinn Tsai; Chih-I Wu (ISLPED, 2017)

Temperature gradient-aware thermal simulator for three-dimensional integrated circuits. - Liang-Ying Lu; Lih-Yih Chiou (IET Comput. Digit. Tech., 2017)

Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme. - Chi-Ray Huang; Kuan-Lin Wu; Chung-Han Wu; Lih-Yih Chiou (ISCAS, 2018)

Fast Steady-State Thermal Analysis. - Lih-Yih Chiou; Chun-Hao Chang; Liang-Ying Lu; Wei-Hsuan Yang; Yeong-Jar Chang; Juin-Ming Lu (ISOCC, 2018)

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation. - Chi-Ray Huang; Lih-Yih Chiou (IET Circuits Devices Syst., 2018)

Methodology for developing virtual platforms from power-aware to power- and thermal-aware at electronic system level. - Liang-Ying Lu; Tsung-Yu Hsieh; Pei-En Weng; Lih-Yih Chiou (IET Cyper-Phys. Syst.: Theory & Appl., 2018)

Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis. - Liang-Ying Lu; Lih-Yih Chiou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM. - Tsai-Kan Chien; Lih-Yih Chiou; Chi-Shian Chang; Jing-Yu Huang; Chung-Han Wu; Heng-Yuan Lee; Shyh-Shyuan Sheu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Intelligent Policy Selection for GPU Warp Scheduler. - Lih-Yih Chiou; Tsung-Han Yang; Jian-Tang Syu; Che-Pin Chang; Yeong-Jar Chang (AICAS, 2019)

A Reliable Delay-Based Physical Unclonable Function with Dark-Bit Avoidance. - Lih-Yih Chiou; Chung-Han Wu; Po-Cheng Wei (ISCAS, 2019)

A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units. - Lih-Yih Chiou; Chao-Kai Yang; Che-Pin Chang (ISCAS, 2019)

A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. - Lih-Yih Chiou; Chi-Ray Huang; Chang-Chieh Cheng; Jing-Yu Huang; Wei-Suo Ling (VLSI-DAT, 2019)

A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection Technique. - Lih-Yih Chiou; Jing-Yu Huang; Chi-Kuan Li; Chen-Chung Tsai (VLSI-DAT, 2021)

An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM. - Chi-Ray Huang; Lih-Yih Chiou (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator. - Lih-Yih Chiou; Hong-Ming Shih; Shun-Hsiu Hsu; Zu-Cheng Sheng; Soon-Jyh Chang (ISCAS, 2024)

An Effective Neural Network Model Protection Method Against Model Stealing Attacks for Image Classification Applications. - Lih-Yih Chiou; Yu-Hung Lee; Chung-Chieh Chiu; Shun-Hsiu Hsu (ISOCC, 2024)

Fast Performance and Power Profiler for SRAM Compute-in-Memory-based Accelerators. - Lih-Yih Chiou; Hong-Ming Shih; Shun-Hsiu Hsu; Tzung-Jin Tsai (ISOCC, 2024)