Distributed On-Chip Operating System for Network on Chip. - Wei Hu 001; Jianliang Ma; Binbin Wu; Lihan Ju; Tianzhou Chen (CIT, 2010)

Global Register Alias Table: Executing Sequential Program on Multi-Core. - Chunhao Wang; Lihan Ju; Di Wu; Lingxiang Xiang; Wei Hu 001; Tianzhou Chen (CIT, 2010)

Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA. - Jie Yang; Like Yan; Lihan Ju; Yuan Wen; Shaobin Zhang; Tianzhou Chen (CIT, 2010)

Shared Register File Based ILP for Multicore. - Lihan Ju; Wei Hu 001; Lingxiang Xiang; Tianzhou Chen (GreenCom/CPSCom, 2010)

Single Thread Program Parallelism with Dataflow Abstracting Thread. - Tianzhou Chen; Xingsheng Tang; Jianliang Ma; Lihan Ju; Guanjun Jiang; Qingsong Shi (ICA3PP (2), 2010)

PeRex: A Power Efficient FPGA-based Architecture for Regular Expression Matching. - Yuan Wen; Xingsheng Tang; Lihan Ju; Tianzhou Chen (GreenCom, 2011)

Block-based hardware scheduler design on Many-core architecture. - Lihan Ju; Ping Pan; Baixing Quan; Tianzhou Chen; Minghui Wu 001 (ISIE, 2012)