A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. - Yushen Fu; Chengyu Huang 001; Limeng Sun; Weiguang Meng; Xueqing Li 002; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. - Sihao Chen; Chengyu Huang 001; Limeng Sun; Yang Liu; Wenjun Tang; Jiaxuan Fan; Nan Sun 001; Yong Chen 005; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)