A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism. - Lin Li 079; Rui Li 095; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs. - Rui Li 095; Heng Yu 001; Lin Li 079; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy. - Rui Li 095; Lin Li 079; Heng Yu 001; Masahiro Fujita; Weixiong Jiang; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)