Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. - Mike J. G. Lewis; Jim D. Garside; L. E. M. Brackenbury (ASYNC, 1999)

An Instruction Buffer for a Low-Power DSP. - Mike J. G. Lewis; L. E. M. Brackenbury (ASYNC, 2000)

Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. - Mike J. G. Lewis; L. E. M. Brackenbury (ASYNC, 2001)

A Low-Power Self-Timed Viterbi Decoder. - Peter A. Riocreux; L. E. M. Brackenbury; J. Mike Cumpstey; Stephen B. Furber (ASYNC, 2001)

CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones. - Mike J. G. Lewis; Linda E. M. Brackenbury (VLSI Design, 2001)

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications. - Mike J. G. Lewis; Linda E. M. Brackenbury (Des. Autom. Embed. Syst., 2002)

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. - Aristides Efthymiou; W. Suntiamorntut; Jim D. Garside; L. E. M. Brackenbury (ASYNC, 2004)

No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder. - Wei Shao; Linda E. M. Brackenbury (ICECS, 2007)

Lowering power in an experimental RISC processor. - Linda E. M. Brackenbury; Wei Shao (Microprocess. Microsystems, 2007)

Pre-processing of convolutional codes for reducing decoding power consumption. - Wei Shao; Linda E. M. Brackenbury (ICASSP, 2008)

Early stopping turbo decoders: a high-throughput, low-energy bit-level approach and implementation. - Wei Shao; Linda E. M. Brackenbury (IET Commun., 2010)

System-on-Chip Design and Implementation. - Linda E. M. Brackenbury; Luis A. Plana; Jeffrey Pepper (IEEE Trans. Educ., 2010)