An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. - V. Visvanathan; Linda S. Milor (SCG, 1986)

Detection of catastrophic faults in analog integrated circuits. - Linda S. Milor; V. Visvanathan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Computing Parametric Yield Accurately and Efficiently. - Linda Milor; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

Optimal Test Set Design for Analog Circuits. - Linda Milor; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

Minimizing production test time to detect faults in analog circuits. - Linda S. Milor; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Computing Parametric Yield Adaptively Using Local Linear Models. - Mien Li; Linda S. Milor (DAC, 1996)

Is High Frequency Analog DFT Possible? - Bozena Kaminska; Tad A. Kwasniewski; Linda S. Milor; G. Roberts; P. Flahive; Jérôme Wojcik (VTS, 1996)

Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. - Michael Orshansky; Linda Milor; Pinhong Chen; Kurt Keutzer; Chenming Hu (ICCAD, 2000)

Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. - Michael Orshansky; Linda Milor; Pinhong Chen; Kurt Keutzer; Chenming Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A BIST Solution for The Test of I/O Speed. - Cheng Jia; Linda S. Milor (ITC, 2003)

Analysis of the layout impact on electric fields in interconnect structures using finite element method. - Changsoo Hong; Linda Milor; M. Z. Lin (Microelectron. Reliab., 2004)

Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models. - Changsoo Hong; Linda S. Milor; Munkang Choi; Tom Lin (Microelectron. Reliab., 2005)

Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. - Munkang Choi; Linda S. Milor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Modeling of the breakdown mechanisms for porous copper/low-k process flows. - Changsoo Hong; Linda Milor (Microelectron. Reliab., 2007)

Backend dielectric breakdown dependence on linewidth and pattern density. - Linda Milor; Changsoo Hong (Microelectron. Reliab., 2007)

Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. - Seyed-Abdollah Aftabjahani; Linda S. Milor (ISQED, 2008)

Diagnosis of Optical Lithography Faults With Product Test Sets. - Munkang Choi; Linda S. Milor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A BIST Circuit for DLL Fault Detection. - Cheng Jia; Linda S. Milor (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Timing Analysis with Compact Variation-Aware Standard Cell Models. - Seyed-Abdollah Aftabjahani; Linda S. Milor (CSIE (3), 2009)

Fast Variation-Aware Statistical Dynamic Timing Analysis. - Seyed-Abdollah Aftabjahani; Linda S. Milor (CSIE (3), 2009)

Reliable cache design with detection of gate oxide breakdown using BIST. - Fahad Ahmed; Linda S. Milor (ICCD, 2009)

Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements. - Muhammad Bashir; Linda Milor (IEEE Des. Test Comput., 2009)

A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation. - Muhammad Bashir; Linda S. Milor (Microelectron. Reliab., 2009)

A DLL Design for Testing I/O Setup and Hold Times. - Cheng Jia; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Towards a chip level reliability simulator for copper/low-k backend processes. - Muhammad Bashir; Linda S. Milor (DATE, 2010)

Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. - Fahad Ahmed; Linda Milor (VTS, 2010)

Via wearout detection with on-chip monitors. - Fahad Ahmed; Linda Milor (Microelectron. J., 2010)

Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. - Muhammad Bashir; Linda S. Milor; Dae Hyun Kim 004; Sung Kyu Lim (Microelectron. Reliab., 2010)

Impact of irregular geometries on low-k dielectric breakdown. - Muhammad Bashir; Linda Milor; Dae Hyun Kim 004; Sung Kyu Lim (Microelectron. Reliab., 2011)

Impact of NBTI on analog components. - Zhengliang Lv; Linda Milor; Shiyuan Yang (ETS, 2012)

A comparative study of wearout mechanisms in state-of-art microprocessors. - Chang-Chih Chen; Fahad Ahmed; Linda Milor (ICCD, 2012)

Wearout-aware compiler-directed register assignment for embedded systems. - Fahad Ahmed; Mohamed M. Sabry; David Atienza; Linda Milor (ISQED, 2012)

Backend dielectric reliability simulator for microprocessor system. - Chang-Chih Chen; Fahad Ahmed; Dae Hyun Kim 004; Sung Kyu Lim; Linda Milor (Microelectron. Reliab., 2012)

Statistical model of NBTI and reliability simulation for analogue circuits. - Zhengliang Lv; Linda S. Milor; Shiyuan Yang (Microelectron. Reliab., 2012)

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells. - Fahad Ahmed; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2012)

System-level modeling and microprocessor reliability analysis for backend wearout mechanisms. - Chang-Chih Chen; Linda Milor (DATE, 2013)

System-level modeling and reliability analysis of microprocessor systems. - Chang-Chih Chen; Linda Milor (IWASI, 2013)

A Delay Evaluation Circuit for Analog BIST Function. - Zhengliang Lv; Shiyuan Yang; Hong Wang; Linda Milor (IEICE Trans. Electron., 2013)

Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis. - Chang-Chih Chen; Fahad Ahmed; Linda Milor (Microelectron. Reliab., 2013)

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements. - Soonyoung Cha; Chang-Chih Chen; Taizhi Liu; Linda S. Milor (VTS, 2014)

Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells. - Woongrae Kim; Linda Milor (VTS, 2014)

Simulation of system backend dielectric reliability. - Chang-Chih Chen; Muhammad Bashir; Linda S. Milor; Daehyun Kim 004; Sung Kyu Lim (Microelectron. J., 2014)

Backend Dielectric Reliability Full Chip Simulator. - Muhammad Muqarrab Bashir; Chang-Chih Chen; Linda Milor; Dae Hyun Kim 004; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines. - Taizhi Liu; Chang-Chih Chen; Linda S. Milor (ISQED, 2015)

Estimation of remaining life using embedded SRAM for wearout parameter extraction. - Woongrae Kim; Chang-Chih Chen; Taizhi Liu; Soonyoung Cha; Linda Milor (IWASI, 2015)

MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array. - Woongrae Kim; Chang-Chih Chen; Soonyoung Cha; Linda Milor (VTS, 2015)

Panel: Analog/RF BIST: Are we there yet? - Sule Ozev; Linda Milor (VTS, 2015)

Processor-level reliability simulator for time-dependent gate dielectric breakdown. - Chang-Chih Chen; Taizhi Liu; Soonyoung Cha; Linda S. Milor (Microprocess. Microsystems, 2015)

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system. - Soonyoung Cha; Dae Hyun Kim 003; Taizhi Liu; Linda S. Milor (Microelectron. Reliab., 2015)

AVERT: An elaborate model for simulating variable retention time in DRAMs. - Dae Hyun Kim 003; Soonyoung Cha; Linda S. Milor (Microelectron. Reliab., 2015)

Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs. - Dae Hyun Kim 003; Soonyoung Cha; Linda S. Milor (Microelectron. Reliab., 2015)

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown. - Taizhi Liu; Chang-Chih Chen; Soonyoung Cha; Linda Milor (Microelectron. Reliab., 2015)

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems. - Taizhi Liu; Chang-Chih Chen; Woongrae Kim; Linda Milor (Microelectron. Reliab., 2015)

Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms. - Chang-Chih Chen; Linda S. Milor (IEEE Trans. Very Large Scale Integr. Syst., 2015)

SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection. - Taizhi Liu; Chang-Chih Chen; Jiadong Wu; Linda S. Milor (ICCD, 2016)

ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs. - Dae Hyun Kim 003; Linda S. Milor (VTS, 2016)

Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs. - Fahad Ahmed; Linda S. Milor (IEEE Trans. Very Large Scale Integr. Syst., 2016)

System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection. - Chang-Chih Chen; Taizhi Liu; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array. - Woongrae Kim; Chang-Chih Chen; Dae Hyun Kim 003; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2016)

On-line monitoring of system health using on-chip SRAMs as a wearout sensor. - Woongrae Kim; Taizhi Liu; Linda Milor (IOLTS, 2017)

Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs. - Soonyoung Cha; Linda Milor (IWASI, 2017)

A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes. - Dae-Hyun Kim 003; Linda Milor (VTS, 2017)

Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test. - Dae-Hyun Kim 003; Linda Milor (Microelectron. Reliab., 2017)

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits. - Kexin Yang 001; Taizhi Liu; Rui Zhang 048; Dae Hyun Kim 003; Linda Milor (Microelectron. Reliab., 2017)

Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations. - Rui Zhang 048; Taizhi Liu; Kexin Yang 001; Linda Milor (Microelectron. Reliab., 2017)

Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements. - Soonyoung Cha; Taizhi Liu; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems. - Dae-Hyun Kim 003; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology. - Kexin Yang 001; Rui Zhang 048; Taizhi Liu; Dae Hyun Kim 003; Linda Milor (DCIS, 2018)

Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms. - Rui Zhang 048; Kexin Yang 001; Taizhi Liu; Linda Milor (DCIS, 2018)

Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology. - Kexin Yang 001; Taizhi Liu; Rui Zhang 048; Linda Milor (VTS, 2018)

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors. - Taizhi Liu; Chang-Chih Chen; Linda Milor (IEEE Trans. Emerg. Top. Comput., 2018)

A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology. - Kexin Yang 001; Taizhi Liu; Rui Zhang 048; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Reliability and Accelerated Testing of 14nm FinFET Ring Oscillators. - Shu-Han Hsu; Kexin Yang 001; Linda Milor (DCIS, 2019)

Identification of Failure Modes for Circuit Samples with Confounded Causes of Failure. - Shu-Han Hsu; Ying-Yuan Huang; Kexin Yang 001; Linda Milor (IOLTS, 2019)

Machine Learning for Detection of Competing Wearout Mechanisms. - Shu-Han Hsu; Kexin Yang 001; Linda Milor (IRPS, 2019)

Impact of Front-End Wearout Mechanisms on the Performance of a Ring Oscillator-Based Thermal Sensor. - Rui Zhang 048; Kexin Yang 001; Taizhi Liu; Linda Milor (IWASI, 2019)

Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown. - Dae-Hyun Kim 003; Shu-Han Hsu; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Inverse Design of FinFET SRAM Cells. - Rui Zhang 048; Zhaocheng Liu; Kexin Yang 001; Taizhi Liu; Wenshan Cai; Linda Milor (IRPS, 2020)

Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation. - Yi-Da Wu; Kexin Yang 001; Shu-Han Hsu; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2020)

SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations. - Rui Zhang 048; Taizhi Liu; Kexin Yang 001; Chang-Chih Chen; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory. - Rui Zhang 048; Kexin Yang 001; Zhaocheng Liu; Taizhi Liu; Wenshan Cai; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2021)

CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration. - Rui Zhang 048; Taizhi Liu; Kexin Yang 001; Linda Milor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)