PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer. - Liangxiao Tang; Weixin Gai; Linqi Shi (ISCAS, 2016)

A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery. - Liangxiao Tang; Weixin Gai; Linqi Shi; Xiao Xiang (ISCAS, 2017)

A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. - Yinxuan Lyu; Jianhua Feng; Chenfeng Tu; Linqi Shi; Hongfei Ye; Weixin Gai; Dunshan Yu (ISCAS, 2018)

A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor. - Linqi Shi; Weixin Gai; Jichao Huang; Liangxiao Tang; Xiao Xiang (ISCAS, 2018)

An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor. - Linqi Shi; Weixin Gai; Xiaoting Zhi; Liangxiao Tang; Xiao Xiang (ISCAS, 2018)

A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. - Liangxiao Tang; Weixin Gai; Linqi Shi; Xiao Xiang; Kai Sheng; Ai He (ISSCC, 2018)

An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation. - Xiao Xiang; Weixin Gai; Linqi Shi; Ai He; Kai Sheng (ISCAS, 2019)

A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET. - Kai Sheng; Linqi Shi; Weixin Gai; Qianting Hua; Peng Lin (ISCAS, 2021)